JPS62154207A - Demodulating circuit - Google Patents

Abstract

PURPOSE:To eliminate an error detection of a discriminating gap pattern by a gap pattern detector of a 2/7 encoding demodulating circuit, by providing a data securing circuit for masking up to a rise of a gap between detecting signal from the gap pattern detector, after having read an input data by a code converting part of a demodulating circuit. CONSTITUTION:A 2/7 code which has been written in a recording medium is read out by an external 2FRD clock by providing a read data gate RDGT, and thereafter, a gap pattern detecting signal GAPDT is detected by a clock VFOCL which has synchronized with a data on a medium, by a gap pattern detector. Until a rise of this signal, the read data gate RDGT and a lock data LDATA are set, and from its result, a period in which a read data enable RDENB is generated is set, and it becomes a range in which a data is not secured. Accordingly, by masking and eliminating this part, the data is secured after the gap pattern detecting signal GAPDT, therefore, an error detection of a head sync byte SB of an identification code ID is eliminated.

Description

[Detailed Description of the Invention] C Overview] The present invention provides a modulation circuit that converts input data into a 2/7 code and writes it to a recording medium at high speed, and a 2/7 code from the recording medium.
A demodulation circuit comprising a 5-code conversion section and a gap pattern detector for detecting a gap turn for address identification at the start of operation; converts the code into output data;
7. In the encoding modulation/demodulation circuit, a data guarantee circuit is provided for masking from the time when the input data is read by the code conversion section of the demodulation circuit to the rising edge of the gap pattern detection signal from the gap pattern detector described above, This ensures the detection of the phase byte at the beginning of the identification code.

[Industrial application field]

The present invention provides a 2/7 magnetic disk drive that converts input data into 2/7 code and writes and reads it at high speed on a recording medium.
The present invention relates to an improvement in data position detection of a demodulation circuit in a /7 encoding f demodulation circuit.

[Conventional technology]

Conventionally, high-speed data writing in magnetic disk devices,
When reading data, the 2/7 encoding method, which has already been proposed, is often used. This is 1, the number of consecutive 0's is 2 or more and 7 or less, leaving 1 '0' and '1'.
This is intended to reduce the occurrence of errors due to high-speed writing by converting to an 8-pit 277 code that excludes the code.

FIG. 3 is a schematic explanatory diagram of a magnetic disk drive f1 using such a 2/7 encoding modulation/demodulation circuit. When modulating, input ride data (W) of interface (IP) code (A)
After phase inverting (B) D), it is converted into a 2/7 code as described below in the modulation circuit 2-1 of the 2/7 coding modulation/demodulation circuit 2, and the WD pulse (0) is sent to the read/write circuit 3. , record to disk. Next, during demodulation, 2/7 code clock read data (
RD) (0) is input into the demodulation circuit 2-2, the 2/7 code is converted to the normal inverted code (B), the phase is inverted, and the output read data (几D ) tl-obtain.

Table 1 shows the interface (IP) codes (
A) and its inverted code (B) and 2/7 code (0)
An example of this is shown below.

The data format of the access data is as shown in Figure 5 (α) of Table 1 below, after detecting the disk index (IND) or sector (SEC), the gap (GAPI) pattern all "0 ON" is repeated. Then the preceding identification code (ID) or address of the sync byte (SB) is sent, and then the GAP2
Similarly, 8B of preceding data (DAT
A) is sent, and the next sector (with GAP5 pattern) is sent.
SEC). The above format is in accordance with the interface regulations, but when applying this to a stirrup code, when the GAP pattern is all "00", the 2/7 code has a repeating pattern of "000100" as shown in Table 1. The period is 3r compared to the period r- of 00''.

In addition, when the GAP pattern is all FF, the 2/7 code has a repetition of "1000" and a period of 2τ. Therefore, when a 2/'7 coding modulation/demodulation circuit is used, the GAP pattern on the disc recording is all FF. "FF" is preferable.However, due to the interface regulations for magnetic disk devices, the GAP pattern in the format is mail 1.
00'', the magnetic disk device 1 in FIG.
As shown in the figure, WD (A) is inverted at the front stage of the 2/7 encoding modulation/demodulation circuit (B) and modulated using the reverse logic, and also demodulated using the reverse logic during demodulation, and then inverted at the rear stage of the V7 encoding modulation/demodulation circuit. (B) and transfers the output D (A).B0 false Figure 4 is an explanatory diagram of the configuration of a conventional 277 encoding/demodulating circuit. Figure 5 (
a) to (i) are its operation waveform diagrams.

In FIG. 4, input read data (R1) of 2/'7 code is successively inputted from the recording medium (disk) by the 2FRD clock of the external clock, and the input read data (R1)) of the 2/'7 code is successively inputted to the 8-bit shift register/code converter 11 for 8-bit shift. Expand to register. Then, the code converter converts the 2/7 code into a normal N-Z code, for example. This operation is shown in Figure 5 (α) ~
The timing at the start of the operation shown in the format of (d'), that is, the rise of the read data gate (DGT) #)
After that, the lock data (LDATA) is generated, and the read data enable signal (DENB) is generated in response to the falling edge of the lock data (LDATA).
Starts when set. The converted gap pattern (GAPPT) is sent to the gap pattern detector 12 which is driven by the same 2FRD clock as the shift register/code converter 11, and is detected as shown in FIG.
The RDGT signal and LDAT human signal shown in (C) are
The gap pattern detection signal (GAP) is reset by the reset signal obtained through the ND circuit 13 and shown in (e) of the same figure.
DT) is output. As a result of detecting the gap pattern on the recording medium, the gap pattern detector 12 outputs a clock (VFOOL) synchronized with the data on the medium, which is applied to a flip-flop (FF) 15 as a synchronization clock, and as a set input to an 8-bit shift register. The converted output code pattern (NILZP) from the code converter 11
T), and the gap pattern detection signal (GAPDT) from the gap pattern detector 12 is input as a reset signal.
) A reset signal obtained through the AND circuit 14 is input to the data gate (DGT), and the read data (DATA) in FIG. 5 is taken out from the Q output, and the inverted Read data (* aD
ATA) is removed.

Gap pattern detection is performed as described above,
After the repetition of the "FF" pattern is detected as described above, it is now necessary to detect the sync-by (SB) at the beginning of the address of the identification signal (I).

Conventionally, the gap pattern detector 12 is provided with a gate whose timing is set by a counter of a host controller, as shown in FIG.
SB search is detected as shown in A) SB search (1).

Detection of the first SB of data (DATA) is also performed using a similar gate @. In this manner, high-speed data reading is performed.

[Problem that the invention seeks to solve]

In the above SB detection method, the procedure for setting υ timing by the host controller is quite complicated. As shown in SB search (2), when the read data gate (几DOT) rises, gate θ is set at the same time to detect the first 8B of the ID, and when the ID falls at 9, the gate @ is set at the same time. Detect the first SB of DATA. This simplifies the method of detecting SB, but in this period of θ, before the rise of GAPDT, SB
Since there is no guarantee against erroneous detection, there is always a possibility that SB erroneous detection will occur.

The object of the present invention is to
It is an object of the present invention to provide a demodulation circuit which prevents false detection of identification gap patterns by a Hatern detector.

[Means for solving problems]

In order to achieve the above object, the present invention includes a code converter that converts a 2/7 code from a recording medium into output data, and a gap pattern detector that detects a gear lag pattern for address identification at the start of operation. In a 2/'7 encoding modulation/demodulation circuit comprising a demodulation circuit, data for masking data from the input data read by the code conversion section of the demodulation circuit to the rising edge of the gap pattern detection signal from the gap pattern detector. It is equipped with a guarantee circuit.

[For production]

After reading the 2/7 code and read data gate (DGT) written on the recording medium using an external (2FRD) clock, a gap pattern detector detects the gap using a clock (VFOOL) synchronized with the data on the medium. Detect pattern detection signal (GAPDT). Until the rise of this signal, as shown in FIGS. 5(cL) to (C), (6
) Read data gate (RD()T), (C) Set lock data (LDATA), and from the result (d)
This is a period in which read data enable (RDENB) occurs, and is a range in which data is not guaranteed. Therefore,
By masking and eliminating this part, data is guaranteed after the gap pattern detection signal (OAPDT), so the first sync-by of the identification code (ID))
8B) false detection is eliminated.

〔Example〕

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention.

FIG. 2 is an operational waveform diagram of main parts of the embodiment.

The difference in FIG. 1 from the conventional example shown in FIG. 4 is that a data guarantee circuit 20, which is surrounded by a broken line, is provided. The data guarantee circuit 20 consists of a flip-flop (FF) 21 and a flip-flop (FF) 22, and the FF 21 receives the gap pattern detection signal (
GAPDT) as the set signal, read data gate (
Input DGT) as a reset signal, take out the DATA mask signal from its Q output, input it as a reset signal for the driven FF22 at VF'OOL, input the Q output rate RDATA of FF15 as a set signal, and output The output RD obtained by excluding the masked portion from the output *RDATA in FIG. 4 is extracted as follows.

Figure 2 (α) to (h) are operational waveform diagrams of the main parts, and Figures (α) to (6) are the same as Figure 5 (α) to (e), and their outputs are Inverted output rate [)ATA in the same figure (a)
shall be taken out. Then, the output RL) ATA mask of FF21 in the same figure (g) is used as the reset signal of FF22,
Channel DAT which is the Q output of FF 15 as a set signal
A is input, and the waveform of the output RD (Figure 1) is obtained.

〔Effect of the invention〕

As explained above, according to the present invention, after input data is read in the code conversion section of the demodulation circuit of the 2/7 encoding modulation/demodulation circuit, up to the rise of the gap pattern detection signal from the gap pattern detector. A masking data guarantee circuit is provided. This eliminates masked portions where data is not guaranteed, eliminating false detections after gap pattern detection, and making it possible to reliably detect the next identification code 5118B.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, Fig. 2 is an operational waveform diagram of the main parts of the embodiment of the invention, Fig. 3 is a general explanatory diagram of a magnetic disk device, and Fig. 4 is a diagram of a conventional example. 5 is an operational waveform diagram of a conventional example, in which 1 is a magnetic disk device, 2 is a 2/7 encoding modulation/demodulation circuit, 2-1 is a modulation circuit, 2-2 is a demodulation circuit, 6 is a read/write circuit, 10 is a 2/7 encoding/demodulating circuit, 11 is an 8-bit shift register code converter, 12 is a gap pattern detector, 16
is a NAND AND circuit is an AND circuit, 15, 21.22
denotes an FF, and 20 denotes a data guarantee circuit.

Claims (1)

[Claims] A modulation circuit that converts input data into a 2/7 code and writes it to a recording medium at high speed, a code converter that converts the 2/7 code from the recording medium into output data, and a gap pattern for address identification at the start of operation. In a 2/7 coding modulation/demodulation circuit comprising a gap pattern detector for detecting a gap pattern and a demodulation circuit comprising: A demodulation circuit characterized by having a data guarantee circuit that masks up to the rising edge of a signal.