JPS6217733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix display device in which signal lines and selection lines are formed in a matrix, and active elements are formed at each intersection of the signal lines and selection lines. The aim is to reduce

Due to its low power consumption, liquid crystal display devices have become completely established as displays for watches and calculators.

However, most of the displays used for these are 7-segment number displays or symbol marks, and in today's world of ever more multifunctional displays, there are limits to their display capabilities. . Dot matrix display was conceived against this background and has been put into practical use to some extent. However, since the dot matrix display requires multi-digit multiplex driving, there are problems such as crosstalk between non-selected points and low contrast of selected points, so that it has only been put into practical use in some calculators.

The following display devices are available to solve various problems caused by multiplex driving of liquid crystals. That is, this is a liquid crystal display device in which an active element is formed in each pixel on one of the two substrates of a cell containing liquid crystal. FIG. 1 is an equivalent circuit diagram of one pixel of such a liquid crystal display device. The liquid crystal display device is composed of a selection line 1, a signal line 2, a write transistor 3, a signal holding capacitor 4, and a capacitor 5 formed by a liquid crystal drive electrode. When the selection line 1 is selected, each write transistor 3 of the corresponding pixel is turned on, and the display signal applied to the signal line 2 is stored in the capacitors 4 and 5. When the writing of pixels on the selection line is completed, the next selection line is selected, and display signals are sequentially written to each pixel. Then, after all pixels have been written, the first selection line is selected again, and the operation is repeated.

The write transistor 3 is an ordinary MOS transistor on a single crystal silicon wafer or a thin film transistor (TFT) formed by depositing a CdSe thin film on a glass substrate. Hereinafter, the present invention will be described as a MOS transistor on a single crystal silicon wafer.

In order for the Tf signal to be held for a period from when a selection line is selected until the next selection, Tf<r(C _H
+ _CL ). Here, r is of transistor 3
It is a parallel combined resistance of the OFF resistance r _pFT and the leakage resistance r _LC of the liquid crystal layer. (i.e., r=r _pFF r _LC /ro
_FT +r _LC ) For example, if the pixel dimensions are 150 μm x 100 μm and the thickness of the liquid crystal layer is 8 μm, the capacitance created by the liquid crystal layer is 0.2 ~
Since it is 0.3PF and about r〓10 ¹⁰ Ω, the time constant is about 3ms. The frequency of AC drive of the liquid crystal is usually about 30 Hz, and one selection line is selected twice in one cycle, so Tf = 15 ms. Therefore, the signal cannot be held only by the capacitor created by the liquid crystal layer. Therefore, a signal holding capacitor 4 of about 1.5PF is required. However, normally it would be sufficient to charge only the capacitor formed by the liquid crystal layer and supply only the leakage current of the liquid crystal layer, but in order to maintain the signal, a capacitor with a large capacity is charged and discharged, increasing power consumption. If the signals that charge capacitors 4 and 5 are at the same level each time, the power loss will be reduced, but since AC drive is performed, a different signal is input each time even for still images, so the power consumption increases. Become. When such a liquid crystal display device is used in a portable information device such as a watch, there is a drawback that the battery life is shortened. Therefore, a display device having cells as shown in FIG. 2 was devised.

Namely, the selection line 1 and the selection line 1 carrying a signal having the opposite phase to the selection line 1, the signal line 2, the write transmission gate 6, the inverters 7 and 8, the transmission gate 9, and the segment signal switching transmission gate 10. , 11, a segment ON signal line 12, a segment OFF signal line 13, and a capacitor 5 formed by the liquid crystal layer. At the time of writing, the selection line 1 becomes "H", the transmission gate (hereinafter abbreviated as TG) 6 is turned on, the TG9 is turned off, and the data on the signal line 2 is written to the gate of the inverter 7.

Next, when the writing is completed and the selection line 1 becomes "L", TG6 is turned off and TG9 is turned on, and the data is latched into the circuits of inverters 7 and 8.
If the output of inverter 7 is “L”, TG10 is
ON state, TG11 becomes OFF state, a signal from the ON signal line 12 of the segment is input, and the liquid crystal becomes ON state. Conversely, if the output of inverter 7 is “H”, TG10 is in the OFF state and TG11 is in the OFF state.
The segment is in the ON state, a signal from the OFF signal line 13 of the segment is applied to the liquid crystal, and the liquid crystal is in the OFF state. At this time, the ON and OFF signals of the segments (referred to as E _ON and E _OFF , respectively) and the signal COM applied to the other electrode of the liquid crystal are expressed as shown in FIG. That is, E _ON and E _OFF are rectangular waves with opposite phases, and E _OFF and COM have exactly the same waveform.

Let's consider the above liquid crystal display device as an actual system such as a clock. Figure 4 is a block diagram of the system, with the central processing unit (CPU)
14, read-only memory (ROM) 15, input/output device interface 16 other than display device,
It is composed of a random access memory (RAM) 17, a column driver 18, a row selection decoder 19, a liquid crystal display device 20, a data bus 21, and an address bus 22. The CPU 14 executes various functions according to programs stored in the ROM 15.

Furthermore, various characters, figures, etc. are stored in the ROM. RAM has a function to temporarily store data processed by the CPU, and in particular, there is a group of addresses in which one address corresponds to one pixel on the panel. (This display-only RAM area is called video RAM.) That is, a RAM area is provided corresponding to the pattern of the display device, and data from this area is transferred to the column driver 18 through the data bus 21, as shown in FIG. is supplied to the signal line 2 of. At this time, a code corresponding to the data is supplied to the row decoder 19. Then, selection line 1
is selected and data is input to the memory cell of the corresponding pixel. In this way, there are two memory cells for holding the same data in the RAM 17 and in the display device. This becomes a major cause of an increase in the number of elements constituting the entire system. In particular, this becomes a very big problem when there are major constraints in terms of spatial size and power consumption, such as watches. The present invention has been made in view of these drawbacks, and will be described in detail below.

Since the RAM 17 and the display device 20 have overlapping memory cells that hold the same data, this results in an increase in the number of elements. Therefore, display device 2
It is only necessary that the memory cells in 0 play the role of memory cells in the RAM 17. Display device 2 plays the role of holding display data for each pixel of the display device and sending it to each pixel.
Although the storage cells in RAM 17 are still functioning, the video RAM in RAM 17 has another role. That is, the video RAM is connected to the CPU through the data bus 21.
The CPU processes the data and outputs it to the video RAM. For example, when a pixel moves in the display of a game, etc., the coordinates at a certain time are supplied to the CPU from the video RAM, and the CPU converts this coordinate data into the coordinate data to be displayed at the next time. supply to.

Therefore, in order for the memory cell of each pixel in the display device 20 to function as a video RAM, it must be able to not only input display data from the column driver 18 but also output it to the data bus 21. The present invention is characterized by paying attention to this point and adopting a cell configuration in which data can be extracted from the memory cells of each pixel of the display device 20.

FIG. 5 is an equivalent circuit diagram of one pixel of the liquid crystal display device according to the first embodiment of the present invention. It is roughly the same as the cell configuration of one pixel of the liquid crystal display device shown in Figure 2, but TG
23 and a signal line 24 having an opposite phase to the read selection signal line 24 are added. That is, the output terminal of the inverter 7 and the signal line 2 are connected via the TG 23 controlled by the read selection signal. Therefore, if the signal line 2 is set to a floating state and the read selection signal line 24 is set to H (that is, 24 is set to L),
TG23 is turned on, and the data held in the memory cells of inverters 7 and 8 is sent onto signal line 2. The data is transferred to the data bus 21 through the column driver 18 and supplied to the CPU.

By using a liquid crystal display device with such a cell configuration, the video RAM can be omitted, so the number of elements in the entire system can be reduced. However, in the circuit configuration shown in FIG. 5, reading can only be performed when the signal line 2 is in a floating state. That is, when even one row is being written, data is being supplied from the driver 18, so the signal line 2 is occupied, resulting in a drawback that reading cannot be performed. Watches, in particular, have large restrictions on power consumption, have a low write clock frequency, take a long time to write, and have a short read time, making them difficult to use.

In order to solve this problem, a second embodiment was devised in which FIG. 6 is an equivalent circuit diagram of one pixel. That is, a read signal line 25 running in the column direction is simply added to the cell shown in FIG. Therefore, since the signal line 2 is used exclusively for write signals, reading can be performed regardless of the state of the signal line 2. Read data is transferred to the data bus 21 through a dedicated bus interface.
It is supplied to

By using the liquid crystal display devices of Examples 1 and 2, it is possible to statically drive a matrix display, which conventionally could only be driven by multiplex driving, and it also has low power consumption and a small number of elements. system, and the effects of the present invention are very large.

When implementing the present invention, yield is a problem due to the large number of elements in the IC chip for the panel. In both Examples 1 and 2, the number of elements is 1 per pixel.
If there are 4 elements and the pixel dimensions are approximately 350μm x 250μm, the element density per ^1mm2 is 150 elements, and with current VLSI technology, it is possible to improve yield by designing with sufficient margin. can be achieved. Furthermore, the TG9 can be omitted by designing the output impedance of the inverter 8 to be high.

The operating mode of the liquid crystal used in the liquid crystal panel of the present invention is that one of the substrates is a Si wafer, which does not transmit light and it is difficult to impart polarization properties to the reflective surface. ) mode and dynamic scattering (DSM) mode, but the GH mode would be advantageous in terms of low power consumption.

As described above, by using the present invention, it is possible to reduce the number of elements in a system using a low power consumption matrix liquid crystal display device for small portable devices such as watches, and to promote multi-functionality of small portable devices such as watches. .

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of one pixel of a conventional matrix panel with active elements. 1... Selection line, 2... Signal line, 3... Write transistor, 4... Signal holding capacitor, 5
...A capacitor created by the liquid crystal layer. Figure 2 shows an equivalent circuit for one pixel of a display device that logically holds signals. 6...Writing TG, 7,8...Inverter,
9...TG, 10, 11...TG for segment signal switching, 12...Segment ON signal line, 13...
Segment OFF signal line. Figure 3 is a diagram of the segment ON and OFF signal waveforms in Figure 2 and the voltage waveform applied to the other electrode of the liquid crystal. FIG. 4 is a block diagram of a system using the display device of FIG. 2. 14...CPU, 15...ROM, 16...I/O device interface, 17...RAM, 18...
...Column driver, 19...Row selection decoder, 20...
...Liquid crystal display device, 21...Data bus, 22...
address bus. FIG. 5 is an equivalent circuit for one pixel of Example 1. 23...TG, 24...Read selection signal line. FIG. 6 is an equivalent circuit for one pixel of Example 2. 25...Read signal line.

Claims (1)

[Claims] 1 A liquid crystal is sealed in a pair of substrates, a plurality of data signal lines and a plurality of selection lines are arranged in a matrix on one of the substrates, and a plurality of data signal lines and a plurality of selection lines are arranged at each intersection of the plurality of data signal lines and the plurality of selection lines. A liquid crystal display device comprising a liquid crystal drive electrode formed, a data signal holding means directly connected to the liquid crystal drive electrode, and a switch means for supplying a data signal from the data signal line to the data signal holding means. , gate means for reading out the data signal held in the data signal holding means by an instruction signal from the external control means, data signal supply means for supplying the data signal from the gate means to the external control means, A liquid crystal display device comprising a selection signal line that supplies the gate means.