JPS62183155A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62183155A JPS62183155A JP61024817A JP2481786A JPS62183155A JP S62183155 A JPS62183155 A JP S62183155A JP 61024817 A JP61024817 A JP 61024817A JP 2481786 A JP2481786 A JP 2481786A JP S62183155 A JPS62183155 A JP S62183155A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- pad
- die pad
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/475—Capacitors in combination with leadframes
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分身〕
この発明は、半導体集積回路装置に係り、特にチップを
固定するダイパッド部分の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a die pad portion for fixing a chip.
第2図tal (blは従来の半導体集積回路装置にお
けるフレームとチップ部分の構成を示す平面図及び断面
図である。FIG. 2 is a plan view and a sectional view showing the structure of a frame and a chip portion in a conventional semiconductor integrated circuit device.
図において、IIIはチップ、(21は前記チップfi
+をフレームに固定させるだめの接着部分、(3)はダ
イパッドである。In the figure, III is a chip (21 is the chip fi)
The adhesive part (3) used to fix the + to the frame is a die pad.
接着部分(2)の材質は導電性のものを使用し、ダイパ
ッド(3)を接地させチップ(1)である半導体集積回
路基板を接地させる。A conductive material is used for the adhesive portion (2), and the die pad (3) is grounded to ground the semiconductor integrated circuit board, which is the chip (1).
また一般に半導体集積回路装置を実装する場合、電源系
の雑音対策として、前記半導体集積回路装置の電源と接
地の間に、バイパスコンデンサと呼ばれるコンデンサを
入れることが多い。Further, when a semiconductor integrated circuit device is generally mounted, a capacitor called a bypass capacitor is often inserted between the power source of the semiconductor integrated circuit device and ground as a countermeasure against noise in the power supply system.
このコンデンサを使用する場合は、挿入する電源・接地
間にできるだけ短い配線で行なう方が効果が大きい。When using this capacitor, it is more effective to use the shortest wiring possible between the power supply and ground.
前記のように、従来の手段で雑音対策を行ないながら、
半導体集積回路装置を実装するには、半導体集積回路装
置を実装したプリント基板などに、コンデンサも実装し
なければならず、実装素子が多くなるため高密度実装の
効率が悪く、又コスト的にも高くなるなどの問題点があ
った。As mentioned above, while taking noise countermeasures using conventional means,
In order to mount a semiconductor integrated circuit device, a capacitor must also be mounted on the printed circuit board on which the semiconductor integrated circuit device is mounted, which increases the number of mounted elements, making high-density mounting inefficient and cost-effective. There were problems such as high prices.
この発明は上記のような問題点を解消するためになされ
たもので、雑音に強い半導体集積回路装置を得ることを
目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device that is resistant to noise.
この発明に係る半導体集積回路装置は、フレームのダイ
パッド部が絶縁物をはさんだ複数の金属板で構成された
ものである。In the semiconductor integrated circuit device according to the present invention, the die pad portion of the frame is composed of a plurality of metal plates sandwiching an insulator.
この発明における半導体集積回路装置は、この半導体集
積回路装置内のダイパッド部にコンデンサを設けること
により、コンデンサが占有する空間を小さくできると共
に、チップとコンデンサの配線長が非常に短かくなる。In the semiconductor integrated circuit device of the present invention, by providing a capacitor in the die pad portion within the semiconductor integrated circuit device, the space occupied by the capacitor can be reduced, and the wiring length between the chip and the capacitor can be extremely shortened.
。
〔実施例〕
第1図+al fblはこの発明の一実施例を示す半導
体集積回路装置のチップとフレーム部分の平面図及び断
面図である。. [Embodiment] FIG. 1 is a plan view and a sectional view of a chip and a frame portion of a semiconductor integrated circuit device showing an embodiment of the present invention.
第2図と同一符号は同一のものである。The same symbols as in FIG. 2 are the same.
第1図において、tl+はチップ、121はチップ11
)をフレームに固定するための導電性がある接着部分、
(3;はチップ+11を固定する上部ダイパッド、(4
)は絶縁層、(6)は下部ダイパッドである。In FIG. 1, tl+ is a chip, 121 is a chip 11
) to the frame, conductive adhesive part,
(3; is the upper die pad that fixes the chip +11, (4;
) is an insulating layer, and (6) is a lower die pad.
図からもわかるように上部ダイパッド(31と同様の下
部ダイパッド(51ヲ設け、それぞれ2つのダイパッド
+31 +51で絶縁層14+をはさむサンドインチ構
造を形成している。As can be seen from the figure, an upper die pad (31) and a lower die pad (51) similar to each other are provided, forming a sandwich structure in which the insulating layer 14+ is sandwiched between the two die pads +31 and +51.
また上部ダイパッド(3)は接地、下部ダイパッド(6
)は電源にそれぞれ接続される。Also, the upper die pad (3) is grounded and the lower die pad (6
) are respectively connected to the power supply.
前記構造よりわかるように、上部ダイパッド(31、絶
縁層+41、下部ダイパッド(6)でコンデンサを形成
しており、またそれぞれの電極となるダイパッド(3)
、(5)は、それぞれ接地及び電源に接続されているた
め、電源・接地間にコンデンサを形成していることにな
る。As can be seen from the above structure, a capacitor is formed by the upper die pad (31), the insulating layer +41, and the lower die pad (6), and the die pad (3) serves as each electrode.
, (5) are connected to the ground and the power supply, respectively, so that a capacitor is formed between the power supply and the ground.
上記実施例では、コンデンサの絶縁層を1層にしている
が、多層構造による積層コンデンサを形成してもよい。In the above embodiment, the insulating layer of the capacitor is one layer, but a multilayer capacitor having a multilayer structure may be formed.
以上のように、この発明によれば、フレームのダイパッ
ド部を絶縁物をはさんだ複数の金属板で構成したので、
雑音に対する半導体集積回路装置の性能が向上し、また
半導体集積回路装置の実装の際、高密度実装化が可能と
なる効果がある。As described above, according to the present invention, the die pad portion of the frame is composed of a plurality of metal plates sandwiching insulators, so that
This has the effect of improving the performance of the semiconductor integrated circuit device against noise and enabling high-density packaging when mounting the semiconductor integrated circuit device.
第1図(Ll (blはこの発明の一実施例による半導
体集積回路装置のチップ・フレーム部の平面図及び断面
図で、第2図+ILI (t)Iは従来の半導体集積回
路装置のチップ・フレーム部の平面図及び断面図である
。
+11はチップ、(21は接着部分、(31は上部ダイ
パッド、(41は絶縁層、(6)は下部ダイパッドであ
る。。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 (BL is a plan view and a sectional view of a chip frame portion of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 +ILI (t)I is a chip frame portion of a conventional semiconductor integrated circuit device. They are a plan view and a cross-sectional view of the frame part. +11 is a chip, (21 is an adhesive part, (31 is an upper die pad, (41 is an insulating layer, and (6) is a lower die pad. In addition, the same reference numerals are used in the figure. indicate the same or equivalent part.
Claims (1)
イパッド部が、絶縁物をはさんだ複数の金属板で構成さ
れていることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device characterized in that a die pad portion of a frame to which a semiconductor integrated circuit chip is die-bonded is composed of a plurality of metal plates sandwiching an insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61024817A JPS62183155A (en) | 1986-02-06 | 1986-02-06 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61024817A JPS62183155A (en) | 1986-02-06 | 1986-02-06 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183155A true JPS62183155A (en) | 1987-08-11 |
Family
ID=12148739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61024817A Pending JPS62183155A (en) | 1986-02-06 | 1986-02-06 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09167823A (en) * | 1996-11-27 | 1997-06-24 | Toshiba Corp | Semiconductor device |
| US5834832A (en) * | 1994-06-09 | 1998-11-10 | Samsung Electronics Co., Ltd. | Packing structure of semiconductor packages |
-
1986
- 1986-02-06 JP JP61024817A patent/JPS62183155A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834832A (en) * | 1994-06-09 | 1998-11-10 | Samsung Electronics Co., Ltd. | Packing structure of semiconductor packages |
| JPH09167823A (en) * | 1996-11-27 | 1997-06-24 | Toshiba Corp | Semiconductor device |
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