JPS6219751U - - Google Patents

Info

Publication number
JPS6219751U
JPS6219751U JP1985111171U JP11117185U JPS6219751U JP S6219751 U JPS6219751 U JP S6219751U JP 1985111171 U JP1985111171 U JP 1985111171U JP 11117185 U JP11117185 U JP 11117185U JP S6219751 U JPS6219751 U JP S6219751U
Authority
JP
Japan
Prior art keywords
substrate
chip
printed wiring
wiring board
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985111171U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985111171U priority Critical patent/JPS6219751U/ja
Publication of JPS6219751U publication Critical patent/JPS6219751U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
JP1985111171U 1985-07-19 1985-07-19 Pending JPS6219751U (2)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985111171U JPS6219751U (2) 1985-07-19 1985-07-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985111171U JPS6219751U (2) 1985-07-19 1985-07-19

Publications (1)

Publication Number Publication Date
JPS6219751U true JPS6219751U (2) 1987-02-05

Family

ID=30990845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985111171U Pending JPS6219751U (2) 1985-07-19 1985-07-19

Country Status (1)

Country Link
JP (1) JPS6219751U (2)

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