JPS62197878U - - Google Patents
Info
- Publication number
- JPS62197878U JPS62197878U JP8739686U JP8739686U JPS62197878U JP S62197878 U JPS62197878 U JP S62197878U JP 8739686 U JP8739686 U JP 8739686U JP 8739686 U JP8739686 U JP 8739686U JP S62197878 U JPS62197878 U JP S62197878U
- Authority
- JP
- Japan
- Prior art keywords
- positioning
- circuit board
- printed circuit
- lead terminal
- flat package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 4
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図面は本考案の一実施例を示すもので、第１図
は本考案の第１の実施例の実装構造を示す斜視図
、第２図は第２の実施例の実装構造を示す斜視図
、第３図は第２の実施例の実装状態を示す正断面
図、第４図は第３実施例の実装構造を示す斜視図
、第５図は第３実施例の実装状態を示す正断面図
、第６図は従来の実装構造を示す斜視図である。
１……フラツトパツケージＩＣ、２……リード
端子、３……プリント基板、４……導体パターン
、５……位置決め用リード端子、６……スルーホ
ール（位置決め用凹所）、７……位置決め用凹所
。
The drawings show an embodiment of the present invention; FIG. 1 is a perspective view showing the mounting structure of the first embodiment of the invention, FIG. 2 is a perspective view showing the mounting structure of the second embodiment, FIG. 3 is a front sectional view showing the mounting state of the second embodiment, FIG. 4 is a perspective view showing the mounting structure of the third embodiment, and FIG. 5 is a front sectional view showing the mounting state of the third embodiment. , FIG. 6 is a perspective view showing a conventional mounting structure. 1...Flat package IC, 2...Lead terminal, 3...Printed circuit board, 4...Conductor pattern, 5...Lead terminal for positioning, 6...Through hole (recess for positioning), 7...Positioning Recess for use.
Claims (1)
ンの上面に半田付けする面実装用フラツトパツケ
ージＩＣにおいて、前記リード端子のうち少なく
とも２本を他よりも長く下方へ突出させて位置決
め用リード端子とし、プリント基板には前記位置
決め用リード端子に対応する位置にこれを嵌合さ
せるための位置決め用凹所を設け、前記位置決め
用リード端子は位置決め用凹所に挿入して半田付
けし、他のリード端子は導体パターンの上面に半
田付けしたことを特徴とするフラツトパツケージ
ＩＣの実装構造。 (2) 前記位置決め用リード端子がスルーホール
挿入型に形成され、前記プリント基板の位置決め
用凹所がスルーホールである実用新案登録請求の
範囲第(1)項に記載のフラツトパツケージＩＣの
実装構造。 (3) 前記位置決め用リード端子がＵ字状に湾曲
してばね力を備え、前記プリント基板の位置決め
用凹所に圧入保持されることを特徴とする実用新
案登録請求の範囲第(1)項に記載のフラツトパツ
ケージＩＣの実装構造。 (4) 前記位置決め用リード端子がばね力を有す
るＵ字状湾曲部と水平突片とを備え、Ｕ字状湾曲
部が前記プリント基板の位置決め用凹所に圧入保
持されると共に、前記水平突片が前記プリント基
板の位置決め用凹所近傍の導体パターン上に半田
付けされることを特徴とする実用新案登録請求の
範囲第(1)項に記載のフラツトパツケージＩＣの
実装構造。[Claims for Utility Model Registration] (1) In a flat package IC for surface mounting in which lead terminals are soldered to the top surface of a conductor pattern on a printed circuit board, at least two of the lead terminals are arranged downward longer than the others. The printed circuit board is provided with a positioning recess for fitting the positioning lead terminal at a position corresponding to the positioning lead terminal, and the positioning lead terminal is inserted into the positioning recess. A flat package IC mounting structure characterized in that the lead terminals are soldered to the upper surface of the conductor pattern, and the other lead terminals are soldered to the upper surface of the conductor pattern. (2) The flat package IC mounting according to claim 1, wherein the positioning lead terminal is formed into a through-hole insertion type, and the positioning recess of the printed circuit board is a through hole. structure. (3) Utility model registration claim (1), characterized in that the positioning lead terminal is curved in a U-shape, has a spring force, and is press-fitted and held in the positioning recess of the printed circuit board. The mounting structure of the flat package IC described in . (4) The positioning lead terminal includes a U-shaped curved portion having a spring force and a horizontal protrusion, and the U-shaped curved portion is press-fitted and held in the positioning recess of the printed circuit board, and the horizontal protrusion The flat package IC mounting structure according to claim 1, wherein the piece is soldered onto a conductive pattern near a positioning recess of the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8739686U JPS62197878U (en) | 1986-06-09 | 1986-06-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8739686U JPS62197878U (en) | 1986-06-09 | 1986-06-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62197878U true JPS62197878U (en) | 1987-12-16 |
Family
ID=30944566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8739686U Pending JPS62197878U (en) | 1986-06-09 | 1986-06-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62197878U (en) |
-
1986
- 1986-06-09 JP JP8739686U patent/JPS62197878U/ja active Pending
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