JPS62199042A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS62199042A JPS62199042A JP4240886A JP4240886A JPS62199042A JP S62199042 A JPS62199042 A JP S62199042A JP 4240886 A JP4240886 A JP 4240886A JP 4240886 A JP4240886 A JP 4240886A JP S62199042 A JPS62199042 A JP S62199042A
- Authority
- JP
- Japan
- Prior art keywords
- insulator
- resistor
- hybrid integrated
- integrated circuit
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
混成集積回路基板上に抵抗体膜を形成する混成集積回路
の製造方法であって、面積抵抗値の異なる抵抗体を絶縁
体を介して積層し、この絶縁体を超音波洗浄により除去
することによって、抵抗値の異なる多種類の抵抗体膜を
形成することができる。[Detailed Description of the Invention] [Summary] A method for manufacturing a hybrid integrated circuit in which a resistor film is formed on a hybrid integrated circuit board, in which resistors having different sheet resistance values are laminated via an insulator, and the By removing the body by ultrasonic cleaning, many types of resistor films with different resistance values can be formed.
本発明は、混成集積回路の製造方法に係り、とくに面積
抵抗値の異なる多種類の抵抗体膜を形成するようにした
混成集積回路の製造方法に関する。The present invention relates to a method for manufacturing a hybrid integrated circuit, and more particularly to a method for manufacturing a hybrid integrated circuit in which many types of resistor films having different sheet resistance values are formed.
近年、電子部品は高集積化技術の驚異的な進展に伴なっ
て、著しく小型化された。ところがこれらの電子部品と
回路を構成する基板上に形成される部品、たとえば抵抗
体等はその抵抗値が高くなると抵抗体の占める面積が非
常に大きくなるので、電子部品に対応し小形で多種類の
抵抗体膜を形成できる混成集積回路の製造方法の開発が
強く要望されている。In recent years, electronic components have become significantly smaller due to the amazing progress in highly integrated technology. However, when the resistance value of components formed on the substrate that constitutes these electronic components and circuits, such as resistors, increases, the area occupied by the resistors becomes extremely large. There is a strong demand for the development of a method for manufacturing hybrid integrated circuits that can form a resistor film of 200 nm.
従来の混成集積回路の製造方法における抵抗体の形成は
、薄膜基板に一種類の低い面積抵抗値の抵抗体膜を形成
し、抵抗値の高い物は微細パターンで形成する方法ある
いは、化成工程を数回に分けて形成していた。In conventional methods for manufacturing hybrid integrated circuits, resistors are formed by forming one type of resistor film with a low sheet resistance value on a thin film substrate, and forming resistors with a high resistance value using a fine pattern or by using a chemical formation process. It was formed in several parts.
上記従来の混成集積回路の製造方法における抵抗体の形
成、すなわち低い面積抵抗値一種類で形成する抵抗体膜
は、所用抵抗値が数１０にΩとなる場合に抵抗体の占め
る面積が非常に大きくなる。Forming a resistor in the above-mentioned conventional hybrid integrated circuit manufacturing method, that is, forming a resistor film with a single type of low area resistance, requires a very large area when the required resistance is several tens of ohms. growing.
また高い面積抵抗値で形成する場合には逆に低い抵抗体
の面積が非常に天き（なり、高密度実装を阻害するとい
う問題がある。あるいは低い面積抵抗値で化成工程を数
回に分けて形成する方法にあっては、コスト高になると
いうそれぞれの問題点があった。On the other hand, when forming with a high sheet resistance value, the area of a low resistor becomes extremely large (which hinders high-density packaging.Alternatively, with a low sheet resistance value, the chemical formation process is divided into several steps). However, the methods of forming the same have the problem of high cost.
本発明は、上記の問題点を解決して低コスト化。 The present invention solves the above problems and reduces costs.
高密度実装化を可能にした混成集積回路の製造方法を提
供するものである。The present invention provides a method for manufacturing a hybrid integrated circuit that enables high-density packaging.
すなわち、混成集積回路を構成する抵抗体の形成を、回
路基板上に面積抵抗値の異なる抵抗体膜を絶縁体を介し
て積層し、前記絶縁体を除去して多種類の面積抵抗体膜
を形成するようにしたことよって解決される。That is, the formation of resistors constituting a hybrid integrated circuit involves stacking resistor films with different sheet resistance values on a circuit board via insulators, and removing the insulators to form various types of sheet resistor films. The problem is solved by making it form.
上記混成集積回路の製造方法は、異なる面積抵抗値の抵
抗体をスパッタ等により絶縁体を介して積層し、超音波
洗浄等により絶縁体を除去して抵抗体膜を形成するもの
で、小面積の抵抗体膜が形成できる。The method for manufacturing the above-mentioned hybrid integrated circuit is to stack resistors with different area resistance values via an insulator by sputtering, etc., and remove the insulator by ultrasonic cleaning to form a resistor film, which has a small area. A resistor film can be formed.
第１図は、本発明方法の一実施例を説明する製造工程を
説明する側断面図である。FIG. 1 is a side sectional view illustrating the manufacturing process of an embodiment of the method of the present invention.
第１図＜６）は、セラミック等からなる薄膜の回路基板
１の一方の面に回路と抵抗体膜となる部分を除き絶縁体
２を印刷乾燥したのち、この絶縁体膜２上に、高い面積
抵抗値を有する例えば窒化タンタルアルミニューム等を
スパッタにより抵抗体膜３を形成する。In Fig. 1<6), an insulator 2 is printed and dried on one side of a thin-film circuit board 1 made of ceramic or the like, excluding the parts that will become the circuit and resistor film, and then a high The resistor film 3 is formed by sputtering a material such as tantalum aluminum nitride having a sheet resistance value.
第１図（ｂ）は、高い面積抵抗値の抵抗体膜３を形成し
たのち、高い抵抗体膜として残す部分に絶縁体２′を印
刷乾燥する。In FIG. 1(b), after forming a resistor film 3 with a high sheet resistance value, an insulator 2' is printed and dried on the portion to be left as a high resistance film.
第１図（Ｃ）は、抵抗体膜３の所定位置に絶縁体２′を
印刷形成した抵抗体Ｉｌｌ ａ上に、低い面積抵抗値の
例えば窒素タンタル等をスパッタにより抵抗体膜４を形
成する。In FIG. 1(C), a resistor film 4 is formed by sputtering, for example, nitrogen tantalum having a low sheet resistance value, on a resistor Illa with an insulator 2' printed at a predetermined position of the resistor film 3. .
第１図（ｄｌは、高い面積抵抗値の抵抗体膜３と低い抵
抗体膜４を積層した抵抗体膜として残す部分に、絶縁体
２″を印刷乾燥する。In FIG. 1 (dl), an insulator 2'' is printed and dried on a portion that remains as a resistor film in which a resistor film 3 with a high sheet resistance value and a resistor film 4 with a low sheet resistance value are laminated.
さらに第１図（ｅ）は、抵抗体膜４の所定位置に絶縁体
２″を印刷形成した抵抗体膜４上に、ニッケルクローム
等からなる中間層５を蒸着し、さらに該中間層５上に金
等からなる上部導体６の蒸着を行なう。Further, in FIG. 1(e), an intermediate layer 5 made of nickel chrome or the like is deposited on the resistor film 4 on which an insulator 2'' is printed at a predetermined position of the resistor film 4, and further on the intermediate layer 5. Then, an upper conductor 6 made of gold or the like is deposited.
そうして、超音波洗浄等により絶縁体２，２′２′をそ
れらの上部の抵抗体膜、導体等と共に除去すれば、第１
図（ｆ）の如く多種類の面積抵抗値を有する抵抗膜膜が
形成された混成集積回路基板とてなる。Then, if the insulators 2, 2'2' are removed together with the resistor film, conductor, etc. on top of them by ultrasonic cleaning etc., the first
As shown in Figure (f), a hybrid integrated circuit board is formed on which resistive films having various sheet resistance values are formed.
第２図は、本発明方法の混成集積回路基板の平面図であ
る。FIG. 2 is a plan view of a hybrid integrated circuit board according to the method of the present invention.
図において、回路基板１上に多種類の抵抗体膜すなわち
高抵抗体膜３．低抵抗体膜４が形成される。In the figure, there are many types of resistor films, that is, high-resistance films 3. A low resistance film 4 is formed.
以上の説明から明らかなように、本発明によれば抵抗体
膜の小面積化が実現でき、高密度実装化が期待できると
ともに、コストダウンに極めて有効である。As is clear from the above description, according to the present invention, the area of the resistor film can be reduced, high-density packaging can be expected, and it is extremely effective in reducing costs.
第１図は、本発明方法の一実施例を説明する製造工程を
説明する側断面図、
第２図は、本発明方法の混成集積回路基板の平面図であ
る。
図において、１は回路基板、２は絶縁体、３は高抵抗体
膜、４は低抵抗体膜、５は中間層、６はｔｂ
２ト湧５日月ブ１；をり一歩ミ２デシｆゴ＠ １ 図
第４餐明万込／）回吋Ｈ巻某ｂ〒旬図
第２図FIG. 1 is a side sectional view illustrating the manufacturing process of an embodiment of the method of the present invention, and FIG. 2 is a plan view of a hybrid integrated circuit board of the method of the present invention. In the figure, 1 is a circuit board, 2 is an insulator, 3 is a high-resistance film, 4 is a low-resistance film, 5 is an intermediate layer, and 6 is a tb. f go @ 1 Figure 4 Meishinmangome/) Volume H certain b〒Shunzu Figure 2
Claims (1)
１）上に面積抵抗値の異なる抵抗体膜（３）、（４）を
絶縁体（２）を介して積層し、 前記絶縁体（２）を除去して多種類の面積抵抗体膜を形
成するようにしたことを特徴とする混成集積回路の製造
方法。[Claims] The formation of a resistor constituting a hybrid integrated circuit is performed on a circuit board (
1) Layer resistor films (3) and (4) with different sheet resistance values on top with an insulator (2) interposed therebetween, and remove the insulator (2) to form various types of sheet resistor films. A method for manufacturing a hybrid integrated circuit, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240886A JPS62199042A (en) | 1986-02-26 | 1986-02-26 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240886A JPS62199042A (en) | 1986-02-26 | 1986-02-26 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199042A true JPS62199042A (en) | 1987-09-02 |
Family
ID=12635239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4240886A Pending JPS62199042A (en) | 1986-02-26 | 1986-02-26 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199042A (en) |
-
1986
- 1986-02-26 JP JP4240886A patent/JPS62199042A/en active Pending
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