JPS62199046A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS62199046A JPS62199046A JP4039086A JP4039086A JPS62199046A JP S62199046 A JPS62199046 A JP S62199046A JP 4039086 A JP4039086 A JP 4039086A JP 4039086 A JP4039086 A JP 4039086A JP S62199046 A JPS62199046 A JP S62199046A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon layer
- layer
- insulating film
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 70
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 65
- 239000011229 interlayer Substances 0.000 abstract description 14
- 230000007423 decrease Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 12
- 229910052698 phosphorus Inorganic materials 0.000 description 12
- 239000011574 phosphorus Substances 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体素子の製造方法に係り、特に、低不純
物濃度多結晶シリコン層からなる高抵抗素子を絶縁膜の
コンタクトホールを介して高不純物濃度多結晶シリコン
層に接続して形成する方法に関する。Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in which a high-resistance device made of a polycrystalline silicon layer with a low impurity concentration is fabricated using a high-resistance device through a contact hole in an insulating film. The present invention relates to a method of forming a layer connected to a doped polycrystalline silicon layer.
（従来の技術）
低不純物濃度多結晶シリコン層からなる高抵抗素子を絶
縁膜のコンタクトホールを介して高不純物濃度多結晶シ
リコン層に接続して形成した半導体素子としては高抵抗
負荷型メモリセルがあシ、その一部の断面図を第１図に
示す。この図において、ｌはシリコン基板、２はゲート
絶縁膜としての酸化膜、３は高ｍ度例えば４〜６ Ｅ２
０ｉｏｎｓ贋のリンをドープしたゲート電極としての第
１の多結晶シリコン層、４は層間絶縁膜、５はコンタク
トホール、６は低濃度例えば１〜９ Ｅ １８ ｔｏｎ
ｓ／ａ１？のリンをドープした高抵抗素子（抵抗値１０
〜１５０ＧΩ／口）としての第２の多結晶シリコン層で
ある。(Prior art) A high resistance load type memory cell is a semiconductor device formed by connecting a high resistance element made of a polycrystalline silicon layer with a low impurity concentration to a polycrystalline silicon layer with a high impurity concentration through a contact hole in an insulating film. A cross-sectional view of a part of the reed is shown in Fig. 1. In this figure, l is a silicon substrate, 2 is an oxide film as a gate insulating film, and 3 is a high degree, for example, 4 to 6 E2.
A first polycrystalline silicon layer as a gate electrode doped with fake phosphorus, 4 is an interlayer insulating film, 5 is a contact hole, 6 is a low concentration, for example 1 to 9 E 18 ton.
s/a1? High resistance element doped with phosphorus (resistance value 10
˜150 GΩ/hole).
ここで、第２の多結晶シリコン層６の両端は、該第２の
多結晶シリコン層６を前述のように高抵抗素子として用
いて、かつ一対の前記第１の多結晶シリコン層３を各々
前述のようにＮＭＯ８のゲート電極として用いてインノ
々−夕を形成するために、前記層間絶縁膜４の各コンタ
クトホールＳを介して前記各第１の多結晶シリコン層３
に接続される。Here, both ends of the second polycrystalline silicon layer 6 are formed using the second polycrystalline silicon layer 6 as a high resistance element as described above, and the pair of first polycrystalline silicon layers 3, respectively. As described above, each of the first polycrystalline silicon layers 3 is inserted through each contact hole S of the interlayer insulating film 4 in order to form an injector for use as a gate electrode of the NMO 8.
connected to.
このような構造体は、従来、次のように製造されている
。まず、シリコン基板１上にゲート絶縁膜となる酸化膜
２を形成した後、ゲート電極となる第１の多結晶シリコ
ン層３を６００〜８００℃。Such a structure has conventionally been manufactured as follows. First, after forming an oxide film 2 that will become a gate insulating film on a silicon substrate 1, a first polycrystalline silicon layer 3 that will become a gate electrode is heated to 600 to 800°C.
０．１〜２Ｔｏｒｒ の圧力中でシランの熱分解によ
シ生成する。その後、この第１の多結晶シリコン層３の
抵抗値を２０〜５０Ω／口に下げるため、該第１の多結
晶シリコン層３にリンを熱拡散により４〜６ Ｅ ２０
１ｏｎｓ％−ドープする。その後、第１の多結晶シリコ
ン層３と酸化膜２を既知のホトリンエツチングを用いて
所望のノぐターン（第１図のパターン）にノぞターニン
グする。その後、ｉ間絶縁膜４１１ｒ：ＣＶＤ法によシ
形成し、この層間絶縁膜４にホトリンエツチングを用い
てコンタクトホール５′ｆｔ形成する。その後、高抵抗
素子となる第２の多結晶シリコン層６を前記第１の多結
晶シリコン層３と同一の方法を用いて生成し、その第２
の多結晶シリコン層６に、所望の抵抗値ｙｆｒ：得るた
めにリンを１〜９ Ｅ １８ ｔｏｎｓ／／イオン打込
みする。It is produced by thermal decomposition of silane at a pressure of 0.1 to 2 Torr. Thereafter, in order to lower the resistance value of the first polycrystalline silicon layer 3 to 20 to 50 Ω/hole, phosphorus is thermally diffused into the first polycrystalline silicon layer 3 to reduce the resistance value to 4 to 6E20.
1 ons%-doped. Thereafter, the first polycrystalline silicon layer 3 and the oxide film 2 are groove-turned into a desired groove pattern (the pattern shown in FIG. 1) using known photolithography. Thereafter, an i-interlayer insulating film 411r is formed by the CVD method, and a contact hole 5'ft is formed in this interlayer insulating film 4 by photolithography. Thereafter, a second polycrystalline silicon layer 6 that becomes a high resistance element is produced using the same method as the first polycrystalline silicon layer 3, and the second polycrystalline silicon layer 6 is
Phosphorus is ion-implanted at 1 to 9 E 18 tons into the polycrystalline silicon layer 6 to obtain a desired resistance value yfr.
その後、既知のホトリソエツチングを用いて第２の多結
晶シリコン層６を所望のノぞターン（第１図のパターン
）にノぞターニングし、さらに９００〜９５０℃の熱処
理を行うことにより第２の多結晶シリコン層６中の不純
物（リン）の活性化を行い、第２の多結晶シリコン層６
を高抵抗素子とする。Thereafter, the second polycrystalline silicon layer 6 is groove-turned into a desired groove turn (the pattern shown in FIG. 1) using known photolithography, and then heat-treated at 900 to 950°C. The impurity (phosphorus) in the polycrystalline silicon layer 6 is activated, and the second polycrystalline silicon layer 6 is activated.
is a high resistance element.
この時、層間絶縁膜４のコンタクトホール５部において
は、第１の多結晶シリコン層３中のリンが第２の多結晶
シリコン層６中へ拡散するので、側条結晶シリコン層３
，６のコンタクト抵抗が下がる。At this time, in the contact hole 5 portion of the interlayer insulating film 4, phosphorus in the first polycrystalline silicon layer 3 diffuses into the second polycrystalline silicon layer 6.
, 6 decreases.
（発明が解決しようとする問題点）
しかるに、上記の従来の方法では、第２の多結晶シＩＪ
コンＦａ６の長さＬが実寸法的に短くなると、前記熱処
理時における第１の多結晶シリコン層３からのリンの拡
散（オート・ドープ）によって第２の多結晶シリコンＮ
Ｉ６の不純物濃度が増加し、ある単位体積当りの不純物
濃度を越えるようになるので、第２の多結晶シリコン層
６のシート抵抗値が急激に低下し、高抵抗素子としての
機能を果せなくなるという問題点があった。(Problems to be Solved by the Invention) However, in the above conventional method, the second polycrystalline IJ
When the length L of the contact Fa6 becomes short in actual dimension, the second polycrystalline silicon N
As the impurity concentration of I6 increases and exceeds a certain impurity concentration per unit volume, the sheet resistance value of the second polycrystalline silicon layer 6 rapidly decreases and it no longer functions as a high resistance element. There was a problem.
この発明は上記の点に鑑みなされたもので、その目的は
、高抵抗素子としての低不純物１１１１度多結晶シリコ
ン層の長さしが実寸法的に短くなっても抵抗の低下を防
ぎ、安定した高抵抗素子を得ることができる半導体素子
の製造方法を提供することにある。This invention was made in view of the above points, and its purpose is to prevent a decrease in resistance and provide stability even if the length of a low impurity 1111 degree polycrystalline silicon layer as a high resistance element becomes shorter in actual dimension. An object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain a high-resistance device.
（間組点を解決するための手段）
この発明では、高不純物濃度多結晶シリコン層（第１の
多結晶シリコン＃）上のコンタクトホールを有する絶縁
膜上に、高抵抗素子材料としての第２の多結晶シリコン
層を形成した後、該第２の多結晶シリコン層に、高抵抗
素子としての抵抗値を得るための不純物さらには、後の
熱処理において前記第１の多結晶シリコン層から拡散さ
れる不純物とほぼ同り度の逆導電型の不純物をイオン打
込みし、その後、第２の多結晶シリコン層中の不純物を
活性化させるための熱処理を行う。(Means for solving interlacing points) In the present invention, a second high-resistance element material is formed on an insulating film having a contact hole on a high impurity concentration polycrystalline silicon layer (first polycrystalline silicon #). After forming the polycrystalline silicon layer, an impurity for obtaining a resistance value as a high resistance element is added to the second polycrystalline silicon layer, which is further diffused from the first polycrystalline silicon layer in a subsequent heat treatment. An impurity of a conductivity type opposite to that of the impurity is ion-implanted, and then heat treatment is performed to activate the impurity in the second polycrystalline silicon layer.
（作 用）
上記熱処理を行うと、第１の多結晶シリコン層から層間
絶縁膜のコンタクトホール部を通して不純物が第２の多
結晶シリコン層に拡散されるが、この不純物は、予め第
２の多結晶シリコン層にイオン打込みしである逆導電型
の不純物とのカウンタードープ現象によシ、電気伝導に
は寄与しなくなる。(Function) When the above heat treatment is performed, impurities are diffused from the first polycrystalline silicon layer into the second polycrystalline silicon layer through the contact hole portion of the interlayer insulating film. Due to a counter-doping phenomenon with an impurity of the opposite conductivity type, which is ion implanted into the crystalline silicon layer, it no longer contributes to electrical conduction.
（実施例）
以下この発明の一実施例を図面を参照して説明する。な
お、この一実施例は、この発明を高抵抗負荷型メモリセ
ルに応用した場合であシ、最終的に得られる構造体は従
来と同一であるから、従来の説明で用いた第１図を利用
してこの発明の一実施例を説明することにする。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. Note that this embodiment is a case where the present invention is applied to a high resistance load type memory cell, and the structure finally obtained is the same as the conventional one, so FIG. An embodiment of the present invention will be explained using the following.
第１図において、１はシリコン基板であシ、まずこのシ
リコン基板ｌ上の全面にゲート絶縁膜となる酸化膜２を
形成する。次に、酸化膜２上の全面に、ゲート電極とな
る第１の多結晶シリコン層３ｆ、６００〜８００°Ｃ、
０，１〜２ Ｔｏｒｒ の圧力中でシランの熱分解に
より生成する。その後、この第１の多結晶シリコン層３
の抵抗値を２０〜５０Ω／口に下げるために、該第１の
多結晶シリコン層３にリンを熱拡散によシ高濃度例えば
４〜６Ｅ２０１ｏｎｓ／Ｊドープする。その後、第１の
多結晶シリコン層３と酸化膜２を既知のホトリソエツチ
ングを用いて所望のノやターンつま夛、第１図のように
一対のゲート電極とその下の一対のゲート絶縁膜を形成
するようにノぞターニングする。In FIG. 1, reference numeral 1 denotes a silicon substrate. First, an oxide film 2, which will become a gate insulating film, is formed on the entire surface of this silicon substrate l. Next, a first polycrystalline silicon layer 3f, which will become a gate electrode, is applied over the entire surface of the oxide film 2 at a temperature of 600 to 800°C.
It is produced by thermal decomposition of silane at a pressure of 0.1-2 Torr. After that, this first polycrystalline silicon layer 3
In order to lower the resistance value to 20 to 50 Ω/hole, the first polycrystalline silicon layer 3 is doped with phosphorus at a high concentration, for example, 4 to 6E201 ons/J, by thermal diffusion. Thereafter, the first polycrystalline silicon layer 3 and the oxide film 2 are formed into desired shapes and turns using known photolithography, and as shown in FIG. 1, a pair of gate electrodes and a pair of gate insulating films thereunder are formed. Turn the groove to form a .
その後、一対のゲート電極としての一対の第１の多結晶
シリコン層３上を含む基板ｌ上の全面を覆うように層間
絶縁膜４をＣＶＤ法により形成し、この層間絶縁膜４に
はホトリソエツチングを用いて前記一対の第１の多結晶
シリコン層３上にてコンタクトホール５を形成する。Thereafter, an interlayer insulating film 4 is formed by the CVD method so as to cover the entire surface of the substrate l including the pair of first polycrystalline silicon layers 3 as a pair of gate electrodes, and this interlayer insulating film 4 is coated with photolithography. Contact holes 5 are formed on the pair of first polycrystalline silicon layers 3 using etching.
その後、層間絶縁膜４上の全面に高抵抗素子材料として
の第２の多結晶シリコン層６を前記嬉１の多結晶シリコ
ン層３と同一の方法を用いて生成する。すると、第２の
多結晶シリコン層６は、層間絶縁膜４のコンタクトホー
ル５部においては該コンタクトホール５を埋めて形成さ
れ、一対の第１の多結晶シリコン層３に接続されるよう
になる。Thereafter, a second polycrystalline silicon layer 6 as a high-resistance element material is formed on the entire surface of the interlayer insulating film 4 using the same method as that for forming the first polycrystalline silicon layer 3. Then, the second polycrystalline silicon layer 6 is formed in the contact hole 5 portion of the interlayer insulating film 4 by filling the contact hole 5, and is connected to the pair of first polycrystalline silicon layers 3. .
次いで、第２の多結晶シリコン層６に、高抵抗素子とし
ての所望の抵抗値を得るためにリンを低濃度例えば１〜
９ Ｅ １８ ｔｏｎｓ／ｃｎ？イオン打込みする。Next, in order to obtain the desired resistance value as a high resistance element, the second polycrystalline silicon layer 6 is doped with phosphorus at a low concentration, e.g.
9 E 18 tons/cn? Implant ions.
その後、続けてＰ型不純物例えばボロンを１〜９Ｂ １
７１ｏｎｓ／ｃｒ！第２の多結晶シリコン層６にイオン
打込みする。その後、既知のホトリンエツチングを用す
て第２の多結晶シリコン層６を所望のノぐターンつまシ
、第１図のように両端が層間絶縁膜４のコンタクトホー
ル５を通して一対の第１の多結晶シリコン看３に接続さ
れた高抵抗素子ノぞターンにノぐターニンクスる。After that, a P-type impurity such as boron is added to 1 to 9B 1
71oz/cr! Ions are implanted into the second polycrystalline silicon layer 6. Thereafter, using known photo-etching, the second polycrystalline silicon layer 6 is etched into desired grooves, and as shown in FIG. The high-resistance element connected to the polycrystalline silicon capacitor 3 is turned on.
そして、その後に、９００〜９５０℃の熱処理をＮ＋雰
囲気中で３０分間行い、第２の多結晶シリコン層６中の
不純物を活性化させることにより、第２の多結晶シリコ
ン層６を高抵抗素子とする。Then, heat treatment at 900 to 950° C. is performed for 30 minutes in an N+ atmosphere to activate impurities in the second polycrystalline silicon layer 6, thereby converting the second polycrystalline silicon layer 6 into a high-resistance element. shall be.
この時、第２の多結晶シリコン層６には、一対の第１の
多結晶シリコン層３から層間絶縁膜４のコンタクトホー
ル５部を通してリンが拡散される。At this time, phosphorus is diffused into the second polycrystalline silicon layer 6 from the pair of first polycrystalline silicon layers 3 through the contact hole 5 portion of the interlayer insulating film 4 .
しかるに、この実施例では、先に第２の多結晶シリコン
層６に、リン（Ｎ型不純物）と逆導電型のボロン（Ｐ型
不純物）をイオン打込みしであるので、前記拡散してき
たリンは、そのボロンとのカウンタードープ現象によ＃
）ｌｌ！気伝導には寄与しなくなる。したがって、この
実施例では、第１の多結晶シリコン層３からのリンの拡
散があっても、第２の多結晶シリコン層６中の電気伝導
に寄与する（抵抗値に関係する）不純物濃度は一定とな
り、その結果、第２の多結晶シリコンＮｉ６の長さＬが
実寸法的に短くなっても、単位体積当りの不純物濃度が
ある一定値を越えることがなくなり、急激なシート抵抗
値の低下が見られなくなる。However, in this embodiment, since phosphorus (N-type impurity) and boron (P-type impurity) of opposite conductivity type are ion-implanted into the second polycrystalline silicon layer 6, the diffused phosphorus is , due to its counterdoping phenomenon with boron #
)ll! It no longer contributes to air conduction. Therefore, in this embodiment, even if phosphorus diffuses from the first polycrystalline silicon layer 3, the impurity concentration that contributes to electrical conduction (related to resistance value) in the second polycrystalline silicon layer 6 is As a result, even if the length L of the second polycrystalline silicon Ni6 becomes shorter in actual dimension, the impurity concentration per unit volume does not exceed a certain value, and the sheet resistance value decreases rapidly. is no longer visible.
第２図および第３図は従来の方法と上記この発明の一実
施例の方法とで、第２の多結晶シリコン層６（高抵抗素
子）の長さＬＴｈ変化させて高抵抗素子を製造した結果
を示す特性図である。第２図の従来方法によれば、長さ
Ｌが６μｍ以下になるとシート抵抗値が急激に低下して
いるが、第３図のこの発明の一実施例の方法によれば、
長さＬが６μｍ以下でもシート抵抗値の急激な低下は見
られず、安定した高抵抗素子が得られている。なお、第
２図および第３図において熱処理温度を変化させても、
高温の万が、多結晶シリコンの粒径の拡大によって抵抗
値の絶対値は低下しているが、長さＬに対する依存性は
各温度においても変化がなく、第３図のこの発明の一実
施例によれば上述した効果が得られている。FIGS. 2 and 3 show high resistance elements manufactured by varying the length LTh of the second polycrystalline silicon layer 6 (high resistance element) using the conventional method and the method according to the embodiment of the present invention. FIG. 3 is a characteristic diagram showing the results. According to the conventional method shown in FIG. 2, the sheet resistance value decreases rapidly when the length L becomes 6 μm or less, but according to the method of an embodiment of the present invention shown in FIG.
Even when the length L is 6 μm or less, no rapid decrease in sheet resistance is observed, and a stable high-resistance element is obtained. Note that even if the heat treatment temperature is changed in FIGS. 2 and 3,
Although the absolute value of the resistance value decreases due to the increase in the grain size of polycrystalline silicon at high temperatures, the dependence on the length L does not change at each temperature, and one implementation of this invention shown in FIG. According to the example, the above-mentioned effects are obtained.
（発明の効果）
以上詳細に説明したようＶＣ１この発明の方法によれば
、高抵抗素子としての低不純物製置多結晶シリコン層の
長さＬが実寸法的に短＜ｉつても抵抗の低下を防ぎ安定
した高抵抗素子を得ることができ、該素子を有する装鐙
のｆ＃度・信頼性を高めることができる。(Effects of the Invention) As described in detail above, according to the method of the present invention, the resistance of the VC1 is reduced even if the length L of the low impurity deposited polycrystalline silicon layer as a high resistance element is short in actual dimension. It is possible to obtain a stable high-resistance element that prevents this, and it is possible to improve the f# degree and reliability of a stirrup equipped with the element.
第１図は高抵抗負荷型メモリセルの一部を示す断面図、
第２図およびＭ３図は従来の方法および本発明一実施例
の方法で高抵抗素子を形成した結果を示す特性図である
。
３・・・第１の多結晶シリコン層、４・・・層間絶縁膜
、５・・・コンタクトホール、６・・・第２の多結晶シ
リコン層。FIG. 1 is a cross-sectional view showing a part of a high resistance load type memory cell.
FIGS. 2 and M3 are characteristic diagrams showing the results of forming high-resistance elements using the conventional method and the method according to an embodiment of the present invention. 3... First polycrystalline silicon layer, 4... Interlayer insulating film, 5... Contact hole, 6... Second polycrystalline silicon layer.
Claims (1)
膜を形成し、この絶縁膜にコンタクトホールを形成する
工程と、 （ｂ）そのコンタクトホールを介して前記第１の多結晶
シリコン層に接続される高抵抗素子材料としての第２の
多結晶シリコン層を前記絶縁膜上に形成する工程と、 （ｃ）その第２の多結晶シリコン層に、高抵抗素子とし
ての抵抗値を得るための不純物さらには、後の熱処理に
おいて前記第１の多結晶シリコン層から拡散される不純
物とほぼ同濃度の逆導電型の不純物をイオン打込みする
工程と、 （ｄ）その後、第２の多結晶シリコン層中の不純物を活
性化させるための熱処理を行う工程とを具備してなる半
導体素子の製造方法。[Scope of Claims] (a) forming an insulating film on a first polycrystalline silicon layer with a high impurity concentration, and forming a contact hole in this insulating film; (b) connecting the (c) forming a second polycrystalline silicon layer as a high-resistance element material connected to the first polycrystalline silicon layer on the insulating film; a step of ion-implanting an impurity to obtain a resistance value as an element, and further an impurity of a conductivity type opposite to that of the impurity diffused from the first polycrystalline silicon layer in a subsequent heat treatment, at a concentration approximately the same; (d) A method for manufacturing a semiconductor device, comprising the steps of: thereafter performing heat treatment to activate impurities in the second polycrystalline silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039086A JPS62199046A (en) | 1986-02-27 | 1986-02-27 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039086A JPS62199046A (en) | 1986-02-27 | 1986-02-27 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199046A true JPS62199046A (en) | 1987-09-02 |
Family
ID=12579328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4039086A Pending JPS62199046A (en) | 1986-02-27 | 1986-02-27 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199046A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6118170A (en) * | 1998-01-13 | 2000-09-12 | Nec Corporation | Resistance element having flexing portion and its manufacturing method |
-
1986
- 1986-02-27 JP JP4039086A patent/JPS62199046A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6118170A (en) * | 1998-01-13 | 2000-09-12 | Nec Corporation | Resistance element having flexing portion and its manufacturing method |
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