JPS6220075Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention uses normalized signals such as 1~5VDC, 4~5VDC,
This invention relates to a signal converter that takes a 20 mADC or the like as an input, determines an arbitrary span using that signal, and outputs a normalized signal corresponding to that span.

FIG. 1 is an explanatory diagram of a circuit configuration of a known signal converter. In Figure 1, the input signal Vi of 1~5VDC
is applied to amplifier U ₁ as a zero base signal by variable resistor RV ₁ . Variable resistor RV ₄ of amplifier U ₁
Any span is expanded with , and the expanded signal is
The voltage across variable resistor RV ₅ is summed in amplifier U ₂ . The output signal of amplifier U ₂ is 4-20 mADC in the current conversion circuit of amplifier U ₃ and transistor T ₁
and output from terminals 5 and 6. Moreover, the 1-5VDC voltage signal is obtained as the voltage across the resistor _R7 inserted in the output circuit. Furthermore, 0~
The 10 mVDC voltage signal is obtained by differentially applying the voltage divided by resistors R ₈ and R ₉ and the voltage by variable resistor RV ₆ to terminals 1 and 2.

Thus, conventional signal converters required three amplifiers and two Zener diodes. Therefore, the circuit configuration has become complicated and expensive.

The present invention is an improvement over the conventional example, and aims to provide a signal converter that has a simple configuration and is inexpensive.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an explanatory diagram of a circuit configuration of a signal converter according to an embodiment of the present invention.

The voltage signal Vi is the voltage signal V _k1 due to the variable resistor RV ₁
A voltage signal V 2 corresponding to the output current Io is applied to one input terminal of the amplifier U ₁ in a differential configuration, and a voltage signal V ₂ corresponding to the output current Io is applied to the other input terminal.

The voltage signal V _k1 is the zener voltage V _D1 of the zener diode D ₁ whose one end is connected to the reference potential point E.
is divided and given by variable resistor _RV1 . In addition, as a voltage signal V ₂ , the output of the amplifier U ₁ is converted into a current Io by the transistor T ₁ , and a resistor R ₁ and a variable resistor RV ₂ are inserted in parallel between the transistor T ₁ and the reference potential point E. A feedback circuit consisting of converts the voltage corresponding to the current Io,
The voltage signal is applied via the variable terminal.

Each output of this circuit is obtained from an output circuit having the following configuration.

The current output Io, for example a 4-20 mADC signal, is obtained from the terminals 5, 6 via a diode _D2 connected in series with the transistor _T1 . Also, voltage output
Vo ₁ , e.g. 1-5VDC signal, is connected to transistor T ₁
It is obtained from terminals 3 and 4 as the voltage across the resistor R ₁ inserted between and the reference potential point E. Furthermore, the zero-based voltage output Vo ₂ , for example 0 to 10 mVDC, is the voltage Vo ₁ formed by two voltage divider circuits that share the resistor R ₃ whose one end is connected to the reference potential point E, that is, the resistors R ₃ and R ₂ . The common voltage dividing point of the voltage dividing circuit of the voltage V _D1 consisting of the voltage dividing circuit and the resistors R ₃ and R ₅ is set to one output terminal 2, and the resistor R ₆ and the variable resistor RV ₃
The voltage dividing terminal of the voltage dividing circuit of the voltage V _D1 consisting of the voltage V D1 is obtained as the other output terminal 1.

Next, the operation of the above circuit will be explained. The numbers assigned to each resistor will be explained below as representing the resistance value of each resistor. It is now assumed that the values of the resistors R ₂ , _{R 3 and} R ₅ are selected so that the relationships R ₃ <<R ₅ and R 3 <<R ₂ are satisfied.

The combined resistance R _A between the transistor T ₁ and the reference potential point E is the variable resistance RV ₂ , the resistance R ₁ and the resistance R ₂
Since it can be regarded as a parallel composite resistance of +R ₃ , R _A becomes equation (1).

R _A = RV ₂ R ₁ (R ₂ + R ₃ ) (1) If amplifier U ₁ is an ideal amplifier, the output current
Io can be expressed by equation (2).

Io = V _i - _{ρ 1} RV ₁ V _D1 / ρ _{2 RA} (2) where ρ ₁ is the voltage division ratio of RV ₁ (0ρ ₁ 1) and ρ ₂ is the voltage division ratio of RV ₂ (0ρ ₂ 1). In equation (2), RV ₁ , V _D1 and _RA are constants, so it can be seen that the bias of Io can be adjusted with ρ ₁ and the span of Io can be adjusted with ρ ₂ .

Now, when the voltage signal Vi=1 to 5VDC, any width of this signal Via to _Vib (1Via< _Vib 5)
The adjustment of ρ ₁ and ρ ₂ will be described below, assuming that the span is converted to an output current Io of 4 to 20 mADC.

Prior to adjusting ρ ₂ , ρ 1 is adjusted so that when Vi=Via (lower limit value of span), Io=0 mADC, _{ρ 1 =} ρ ₁₁ is obtained. Therefore, equation (3) is obtained from the relationship of equation (2).

ρ ₁₁ =Via/RV ₁・V _D1 (3) Next, when Vi=V _ib (upper limit of span), adjust ρ ₂ so that Io=16 mADC, and get ρ ₂ = ρ ₂₁ get. Therefore, equation (4) is obtained from the relationship between equations (2) and (3).

16x10 ^-3 =V _ib -ρ ₁₁・RV ₁・V _D1 /ρ ₂₁
・R _A = V _ib −Via/ρ ₂₁・R _A (4) From equation (4), by setting ρ ₂ to ρ ₂₁ , it corresponds to the voltage signal in the span of V _ib to Via.
It can be seen that Io of 16mADC span can be obtained.

Equation (2) can be expressed as equation (2') using ρ ₁₁ and ρ ₂₁ obtained based on the above adjustment.

Io=Vi−ρ ₁₁・RV ₁・V _D1 /ρ ₂₁・_RA (
2') By the way, since a bias signal of 4 to 20 mADC with a 16 mADC span is required as the output current Io, Io = 4 mADC must hold at Vi = Via, so adjust ρ ₁₁ in equation (2'). If we obtain a value ρ ₁₂ that satisfies the above conditions, the output current will be expressed as equation (2″).

Io=Vi−ρ ₁₂・RV ₁・V _D1 /ρ ₂₁・_RA (
In other words, if the voltage division ratio of the variable resistor RV ₁ is set to ρ ₁₂ and the voltage division ratio of the variable resistor RV ₂ is set to ρ ₂₁ , the current signal Io (4″) whose span is an arbitrary width V _ib to Via of the voltage signal Vi is obtained. ~
20mADC). Therefore,
RV ₁ , R ₁ so that the parallel combined resistance R _A is 250Ω
By selecting the values of and _R2 + _R3 , the voltage output _Vo1 is obtained as a 1-5VDC signal. When making this selection, ensure that R ₁ ≪ RV ₁ , (R ₂ + R ₃ ),
If the resistor R ₁ is made of precision grade, the voltage signal Vo ₁ can be obtained with high accuracy. Note that in order to obtain a voltage signal Vo ₂ to be described later with high precision, precision grade resistors R ₂ and R ₃ are also selected.

Next, a case where 0 to 10 mVDC is obtained as the voltage output Vo ₂ will be explained.

Resistors R ₂ and R ₃ are a voltage divider circuit of voltage Vo ₁ , and
Since the resistors R ₃ and R ₅ are a voltage divider circuit of the voltage V _D1 , the voltage Vo ₃ between terminals 2 and 3 is as follows.

That is, according to the law of superposition, Vo ₃ is expressed as equation (5).

Vo ₃ ≒Vo ₃₁ −Vo ₃₂ (5) However, Vo ₃₁ is the terminal 2 and 3 when Vo ₁ = 0.
Vo ₃₂ is obtained by equation (6) using the voltage between terminals 2 and 3 when V _D1 =0.

Vo ₃₁ ≒R ₃ /R ₃ +R ₅ V _D1 (6) However, R ₃ ≪R ₂ Vo ₃₂ ≒R ₃ /R ₂ +R ₃ Vo ₁ (7) However, R ₃ ≪R ₅ Therefore, variable resistance If the voltage obtained by RV ₃ is V _k3 , the output voltage Vo ₂ between terminals 1 and 2 is expressed by equation (8).

Vo ₂ ≒R ₃ /R ₂ +R ₃ Vo ₁ −R ₃ /R ₃ +R ₅ V _D1 −
V _k3 (8) In equation (8), Vo ₁ is a 1 to 5 VDC signal corresponding to the voltage signal V _ib to Via, V _D1 is constant, and V _k
3 is an adjustable voltage, by selecting the values of resistors R ₂ , R ₃ , R ₅ and the voltage division ratio of RV ₃ so that equations (9) and (10) hold true.
_Vo2 can obtain a voltage signal of 0-10mVDC.

R ₃ /R ₂ +R ₃ Vo ₁ =2.5 to 12.5 mVDC (9) R ₃ /R ₃ +R ₅ V _D1 −V _k3 =2.5 mVDC (10) As explained in detail above, according to the present invention,
Since a simple and inexpensive signal converter with fewer components can be obtained, and there is no interference between the zero adjustment circuit and the span adjustment circuit, it has great effects in this field.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of a conventional signal converter, and FIG. 2 is an explanatory diagram of the configuration of a signal conversion circuit according to an embodiment of the present invention. U ₁ ...Amplifier, T ₁ ...Transistor, R ₁ to _{R 6}
...Resistor, RV ₁ to _{RV 3} ... Variable resistance, D ₁ ... Zener diode.

Claims (1)

[Claims for Utility Model Registration] (1) In a signal converter that receives a normalized voltage signal as an input, converts the voltage signal into a normalized signal with an arbitrary width as a span, and outputs the normalized signal, one of which is an input terminal. , a high input resistance amplifier with the other as a feedback terminal, a transistor that converts the output of the amplifier into a current, and a circuit that is located between the transistor and a reference potential point of the circuit and converts the current into a voltage; a circuit that divides the output voltage of the current/voltage conversion circuit and supplies it to the feedback terminal of the amplifier; a constant voltage circuit comprising a Zener diode having one end connected to a reference potential point of the circuit; and the constant voltage circuit. and a circuit that divides and outputs the output voltage of the transistor, wherein the normalized voltage signal is differentially applied to the divided voltage output of the constant voltage circuit, and the current output of the transistor or the A signal converter characterized in that the voltage output of a current/voltage conversion circuit is obtained as a conversion signal. (2) A circuit that divides the voltage output of the current/voltage conversion circuit is composed of a resistor _R3 and a resistor _R2 , one end of which is connected to the reference potential point of the circuit, and the voltage output of the constant voltage circuit is A variable resistor RV ₃ constitutes a circuit for dividing the voltage of the constant voltage circuit by the resistor R ₃ and the resistor R ₅ , and a circuit for dividing the voltage output of the constant voltage circuit, one end of which is connected to the reference potential point of the circuit.
The voltage dividing output terminal of the voltage dividing circuit consisting of the resistors R ₂ , R ₃ and R ₅ and the variable resistor RV ₃
2. The signal conversion circuit according to item 1, wherein the signal conversion circuit obtains a conversion signal between the variable terminal and the variable terminal.