JPS62201814U - - Google Patents
Info
- Publication number
- JPS62201814U JPS62201814U JP8943686U JP8943686U JPS62201814U JP S62201814 U JPS62201814 U JP S62201814U JP 8943686 U JP8943686 U JP 8943686U JP 8943686 U JP8943686 U JP 8943686U JP S62201814 U JPS62201814 U JP S62201814U
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- voltage
- divider circuit
- transistor
- voltage divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Voltage And Current In General (AREA)
- Electronic Switches (AREA)
Description
図はこの考案の実施例である分圧回路の回路図
である。
ＳＷ……スイツチ（信号発生手段）、Ｑ１……
第一のトランジスタ、Ｑ２……第二のトランジス
タ、Ａ……電源電圧抵抗分圧回路、Ｂ……第一の
基準電圧抵抗分圧回路、Ｃ……第二の基準電圧抵
抗分圧回路。
The figure is a circuit diagram of a voltage dividing circuit which is an embodiment of this invention. SW...Switch (signal generation means), Q1...
First transistor, Q2...Second transistor, A...Power supply voltage resistance voltage divider circuit, B...First reference voltage resistance voltage divider circuit, C...Second reference voltage resistance voltage divider circuit.
Claims (1)
号発生手段からの信号を受ける信号入力端子が中
間点に接続された電源電圧抵抗分圧回路と、それ
ぞれのベース端子が前記電源電圧抵抗分圧回路の
複数の中間点にそれぞれ接続され、前記信号入力
端子が“Ｈ”の時オンする第一のトランジスタお
よび前記信号入力端子が“Ｌ”の時オンする第二
のトランジスタと、前記第一のトランジスタに直
列に接続され基準電圧が印加される第一の基準電
圧抵抗分圧回路と、前記第一の基準電圧抵抗分圧
回路の中間点を共通にし、前記第二のトランジス
タに直列に接続され基準電圧が印加される第二の
基準電圧抵抗分圧回路と、を有し、 前記第一、第二の基準電圧抵抗分圧回路の抵抗
を可変抵抗で構成するとともに、前記第一、第二
の基準電圧抵抗分圧回路の中間点を出力端子に接
続してなる分圧回路。[Claims for Utility Model Registration] An “H” or “L” signal generating means, a power supply voltage resistor voltage divider circuit having a signal input terminal connected to an intermediate point for receiving a signal from the signal generating means, and each A first transistor whose base terminal is connected to a plurality of intermediate points of the power supply voltage resistance voltage divider circuit, and which is turned on when the signal input terminal is "H" and a second transistor whose base terminal is turned on when the signal input terminal is "L". the second transistor, a first reference voltage resistor voltage divider circuit connected in series to the first transistor and to which a reference voltage is applied, and the first reference voltage resistor voltage divider circuit have a common intermediate point; a second reference voltage resistor voltage divider circuit connected in series to the second transistor and to which a reference voltage is applied; the resistors of the first and second reference voltage resistor voltage divider circuits are configured with variable resistors. and a voltage dividing circuit in which a midpoint between the first and second reference voltage resistance voltage dividing circuits is connected to an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8943686U JPS62201814U (en) | 1986-06-11 | 1986-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8943686U JPS62201814U (en) | 1986-06-11 | 1986-06-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62201814U true JPS62201814U (en) | 1987-12-23 |
Family
ID=30948419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8943686U Pending JPS62201814U (en) | 1986-06-11 | 1986-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62201814U (en) |
-
1986
- 1986-06-11 JP JP8943686U patent/JPS62201814U/ja active Pending