JPS62201862U

JPS62201862U -

Info

Publication number: JPS62201862U
Application number: JP3513787U
Authority: JP
Priority date: 1987-03-12
Filing date: 1987-03-12
Publication date: 1987-12-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示すバス接続図、
第２図は第１図のバス上の信号配列を示す図、第
３図は第１図のバスの制御タイミングの一例を示
すタイムチヤート図、第４図は親バス、子バス、
およびバス中継回路の回路構成図である。図において、１は主装置、２はバス制御回路、
３は親バス、４１〜４８はバス中継回路、５１〜
５８は子バス、６１１〜６１８，……，６８１〜
６８８は従装置である。 FIG. 1 is a bus connection diagram showing an embodiment of the present invention.
2 is a diagram showing the signal arrangement on the bus in FIG. 1, FIG. 3 is a time chart showing an example of the control timing of the bus in FIG. 1, and FIG. 4 is a diagram showing the parent bus, child bus,
and a circuit configuration diagram of a bus relay circuit. In the figure, 1 is the main device, 2 is the bus control circuit,
3 is a parent bus, 41 to 48 are bus relay circuits, and 51 to 48 are bus relay circuits.
58 is a child bus, 611~618,...,681~
688 is a slave device.

Claims

[Scope of utility model registration request]

One main device that controls the system including a bus control circuit that controls a bidirectional bus, a parent bus connected to the bus control circuit, a plurality of bus relay circuits connected to the parent bus, and the bus relay The bus relay circuit has a child bus connected to each of the circuits and one or more slave devices connected to each of the child buses, and the bus relay circuit receives a downstream control signal from the bus control circuit and the slave device. 1. A data processing device that performs downlink and uplink data direction control between the parent bus and the child bus, respectively, based on uplink direction control signals from the parent bus and the child bus.