JPS6221128B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to a control method for variable length data instructions in an information processing apparatus.

Conventionally, there have been two types of control methods for processing variable length data in an information processing apparatus that processes variable length data instructions.

(1) Byte processing method in which operand processing is performed in byte units (2) Word processing method in which operand processing is performed in word units The byte processing method in (1) above uses the first operand register for the first operand (operand). means for selecting sequential bytes from a second operand register for a second operand (operand number); It is a control method that performs calculations in byte units, and has a byte calculation circuit that performs various calculations, and a means for storing the output of the byte calculation circuit in the first operand register for the first operand, and requires relatively little hardware. Although it is easy to control, it has the disadvantage that it is unsuitable for high-speed processing when the operand length is relatively large because it processes in bytes.

On the other hand, in the word processing method (2) above, the first operand register for the first operand, the second and third operand registers for the second operand register, and the starting byte position of the first operand and the means for subtracting the difference between the starting byte positions of the two operands; means for inputting the second and third operand registers and shifting by the difference between the starting byte positions of the first and second operands; It has a word operation circuit that inputs two operand registers and processes it in word units.It is a control system that operates in word units, and before starting the operation in word units, the first and second operands are Shifting two operands;
An action is required to clear unnecessary bytes in the operand register. Therefore, even when the operand length is relatively small, the advantage of high-speed processing in word units is lost due to the time required for the preprocessing, and the processing time becomes longer than when executing byte processing in (1) above. There were flaws.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a circuit for sequentially selecting an operand length field of a variable length data instruction from an instruction buffer register for prefetching, and a designation circuit; a comparison circuit for comparing the output of the selection circuit and the output of the operand length designation circuit;
By determining whether variable-length operands are to be controlled by word processing or byte processing at the prefetch stage of the instruction, and by controlling them by byte processing if the operand length is smaller than the operand length specification circuit,
The object of the present invention is to solve the above drawbacks, shorten the execution time when the operand length is smaller than the value set by the operand length designation circuit, and improve information processing performance.

That is, according to the present invention, in an information processing device that processes variable-length data instructions, an instruction buffer register for prefetching and an operand length field of a variable-length data instruction word are sequentially selected from the instruction buffer register. It consists of a selection circuit, an operand length designation circuit, a comparison circuit that compares the output of the selection circuit and the output of the operand length designation circuit, a byte processing control circuit, and a word processing control circuit, and the comparison circuit When it is detected that the output value of the selection circuit is larger than the output value of the operand length designation circuit, control is transferred to the word processing control circuit to perform word processing, and the output value of the selection circuit is determined to be larger than the output value of the operand length designation circuit. There is provided an information processing apparatus characterized in that when it is detected that the output value is smaller than the output value, control is transferred to a byte processing control circuit to perform byte processing.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In Figure 1,
Reference number 1 indicates a memory, and this memory 1 is a storage circuit that stores instruction words and operands. The instruction prefetch buffer register 2 is a register that prefetches and stores up to four preceding instructions. OP
The code and operand length field selection circuit 3 sequentially selects the OP code from the instruction prefetch buffer register 2.
This circuit selects the operand length field.
The operand length designation circuit 4 is set to a constant value when the system is initialized or by a specific command. Comparison circuit 5 compares the output of operand length field selection circuit 3 and the output of operand length designation circuit 4, and the output sets flip-flop 13. OP code register 6 is the OP code,
This is a register in which the OP code field section output of the operand length field selection circuit 3 is stored.
The first control unit control memory 8 is a memory containing the start address and control information of each instruction in the control store 14. The second control unit control memory 9 is a memory containing the start address of a microprogram when a variable length data instruction is executed by byte processing. The read output of the first control unit control memory 8 is stored in the first control unit control memory output register 10. The address to the second control unit control memory 9 is generated by the second control unit control memory address generation circuit 7 from the output of the OP code register 6, and its read output is stored in the second control unit control memory output register 11. The selection circuit 12 is a circuit for selecting the output of either the first control unit control memory output register 10 or the second control unit control memory output register 11. The output of selection circuit 12 is connected to control store 14 . The read output of the control memory 14 is stored in the control point register 15.

The first operand register 17 is a register that reads the first operand of a variable length data instruction from the memory 1 and stores it. 2nd operand register 1
8 and 24 are 8-byte registers each for reading the second operand from the memory 1 and storing it therein. 1st
Operand pointer 16 is a 3-bit counter and specifies a byte position within 8 bytes of second operand register 17. The second operand pointer 19 is a 3-bit counter and specifies the byte position within the second operand register 18. The selection circuit 20 is a circuit that selects one byte designated by the first operand pointer 16 from the first operand register 17. The selection circuit 21 selects the second operand pointer 1 from the second operand register 18.
This circuit selects 1 byte specified by 9. The byte operation circuit 22 is a circuit that receives one byte of output from the selection circuit 20 and one byte of output from the selection circuit 21 and executes various operations such as addition and subtraction, and the output is specified by the first operand pointer 16. is set to the byte location in the first operand register 17. Each time the byte operation is processed one byte at a time, the contents of the first operand pointer 16 and the second operand pointer 19 are updated by +1. The word arithmetic unit 23 inputs the first operand register 17 and the second operand register 18 and performs word operations such as addition and subtraction logical operations.

Next, the operation of this embodiment will be explained using FIGS. 2 and 3. FIG. 2 is a timing chart of this embodiment, and FIG. 3 is a conceptual diagram for explaining microprogram control. Assuming that the instruction word of a variable length data instruction is stored in the instruction buffer register 2, the OP code,
The OP code portion of the operand length field selection circuit 3 is stored in the OP code register 6. Also, OP
Operand length designation circuit 4 in which the operand length field section of the code and operand length field selection circuit 3 is initialized at system initialization.
When the operand length field section 3 is larger than the output of the operand length designation circuit 4, the word processing designation flip-flop 13 is set to "1", and the operand length field section 3 is compared with the output of the operand length designation circuit 4. If it is smaller than the output of the length designation circuit 4, the word processing designation flip-flop 13 is set to "0". At timing T2, the first control unit control memory 8 is accessed by the output of the OP code register 6, and the readout output is sent to the first control unit control memory output register 10.
is stored in The second control unit control memory 9 stores the starting address of a microprogram when variable length data instructions are executed by byte processing. On the other hand, the second control unit control memory 9 stores the start address of a microprogram when a variable length data instruction is executed by byte processing. At timing T2, the output of the second control unit control memory 9 is stored in the second control unit control memory output register 11. At timing T3, when the flip-flop 13 is "1", the selection circuit 12 selects the output of the first control unit control memory output register 10, and when the flip-flop 13 is "0", the selection circuit 12 selects the output of the second control unit control memory output register 10.
The output of the control unit control memory output register 11 is selected, the control store 14 is accessed with the output, and the read output is stored in the control point register 15. The output of control point register 15 is connected to control circuit 25. The output of the control circuit 25 performs various controls, and when the flip-flop 13 is "1",
The word processing circuit 23 is used to control word processing, and when the flip-flop 13 is "0", the byte processing circuit 22 is used to control byte processing. The above operation is shown in FIG. 3, where the start address of the microprogram for word processing is indicated by A, and the start address of the microprogram for byte processing is indicated by A'.

As explained above, the operand length field is compared with the operand length specification circuit at the prefetch stage of the instruction, and if the operand length is larger than the operand length specification circuit, word processing is executed, and the operand length is smaller than the operand length specification circuit. By executing byte processing in some cases, the drawback that the word processing execution time is larger than the byte processing execution time when the operand length is relatively small is eliminated, thus speeding up the execution of variable-length data instructions. It becomes possible to process.

As explained above, the present invention compares the operand length field of a variable-length data instruction with an operand length specification circuit at the instruction prefetch stage, and determines whether the variable-length data instruction is word processing or byte processing based on the output of the comparison circuit. By configuring the processing to be performed using one of the following methods, it is possible to provide an apparatus capable of high-speed processing even when the operand length is small.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation timing chart of the embodiment, and FIG. 3 is a conceptual diagram for explaining microprogram control. 1...Memory, 2...Instruction preemption buffer register, 3...OP code, operand length field selection circuit, 4...Operand length specification circuit, 5...
Comparison circuit, 6... OP code register, 7... Second control unit control memory address generation circuit, 8
...First control unit control memory, 9...Second control unit control memory, 10...First control unit control memory output register, 11...Second control unit control memory output register, 12...Selection circuit, 13 ...Word processing specified flip-flop,
14... Control memory, 15... Control point register, 17... First operand register, 18, 24... Second operand register, 16... First operand pointer, 19...
Second operand pointer, 20...First operand byte selection circuit, 21...Second operand byte selection circuit, 22...Byte operation circuit, 23...
Word operation circuit, 25... Control circuit, 100...
Initial setting value signal.

Claims (1)

[Claims] 1. In an information processing device that processes variable-length data instructions, there is provided an instruction buffer register for prefetching, a selection circuit that selects an operand length field of a sequential variable-length data instruction word from the instruction buffer register, and an operand length specification circuit. a comparison circuit that compares the output of the selection circuit with the output of the operand length designation circuit, a byte processing control circuit, and a word processing control circuit, and the comparison circuit compares the output value of the selection circuit with the output value of the selection circuit. If it is detected that the output value is larger than the output value of the operand length designation circuit, control is transferred to a word processing control circuit to perform word processing, and the output value of the selection circuit is detected to be smaller than the output value of the operand length designation circuit. An information processing device characterized in that when detected, control is transferred to a byte processing control circuit to perform byte processing.