JPS6223155A - Active matrix array panel and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve yield of the titled products on manufacture by forming a semiconductor thin-film used as a switching element in the whole region under a wiring for a signal line as an upper electrode for the switching element and under a terminal. CONSTITUTION:A gate electrode 102 consisting of Cr is shaped onto an insulating substrate 101 composed of soda glass coated with SiO in a patterning manner. A gate insulating film 103 consisting of SiN and an a-Si:H semiconductor film 104 composed of an i layer and an n<+> semiconductor layer 105 are formed onto the gate electrode 102, and a drain electrode 108 and a Cr wiring metal 106 for a source electrode 110 are shaped. A stepped section in the thickness of the gate electrode is only formed in the continuous wiring of the drain electrode, a drain bus line and a terminal electrode, and no stepped section by the film formation ends of the insulation isolation and plasma CVD of a TFT is shaped. Accordingly, disconnections due to the stepped sections of the wiring and disconnections due to peeling can be reduced remarkably, thus cutting down cost, then improving yield on manufacture.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix array panel incorporated into an active matrix liquid crystal display device, etc., and a method for manufacturing the same.

(Conventional method) Active matrix array panels have come to be widely used in liquid crystal display devices in recent years.

Compared to the conventional IJ-Fuchs method, the active matrix method, which has active elements such as thin film transistors and diodes, is widely used because it can display large volumes and improve display characteristics. No way. Typical active elements are amorphous silicon (a-8i) and polysilicon (p-8i).
) is a thin film transistor (TPT) using a thin film transistor (TPT).

For example, FIG. 4 shows a schematic plan view Φ) of a part of a matrix array panel using a-8i TFTs and a schematic cross-sectional view (a) taken along the line AA'.

Conventionally, an a-Si TI+'T matrix array panel was created and constructed as follows. A wiring metal such as chromium is deposited on an insulating substrate 401 such as glass,
The gate electrode 402 is formed by patterning it.

Next, on the substrate 401 on which the gate electrode 402 is formed, a gate insulating film 403 made of silicon nitride (SiN, etc.) and a semiconductor film 404 made of a-Si are sequentially deposited by plasma CVD. 09 layers (
It has two layers including an n+ semiconductor layer 405). n?
The semiconductor layer 405 is provided to improve ohmic contact with the source/drain electrodes, and may not be provided in some cases.

Next, to matrix TPT, each TF'r
The deposited semiconductor 840
4 is masked and removed by etching to insulate and isolate it in a plane. As a result, the gate insulating film 403 remains in the deposited region, but the region where the semiconductor 404 is present is the TFT 4.
12 of the semiconductor region 413.

Note that the film forming end 414 of the deposited region is the gate insulating film 4.
A large step difference occurs due to the respective film thicknesses of the semiconductor film 404 and the semiconductor film 404. Further, in the mask process, etching residues 415 may be formed at this step due to overlapping of mask patterns. - The male conductor region 413 may be expanded to the point where the gate electrode 402 intersects with the drain line 406 to improve the insulation between the electrodes.

As the next step, a metal 406 for drain electrode wiring is deposited and turned to form a source electrode 410, a drain electrode 408, and a drain pass line 416. At that time, only etching the wiring metal 406 (
, the unnecessary n9 semiconductor layer 405 in the TPT 412 portion is also removed by etching using the same mask.

Next, indium tin oxide fi (ITO film) 407 etc. (
7) A 4-electrode film is deposited to serve as a display electrode 411, and patterned so that the matrix-like display electrode 411 is connected to the source electrode 410 of the TFT 412.

At this time, if the engineered gamma film 407 is removed by etching using a mask pattern that also remains on the drain electrode 408, drain pass line 416, and drain terminal electrode 409, the drain wiring resistance can be reduced. The TPT matrix array panel produced through the above steps has a cross-sectional structure as shown in FIG. 4(a).

(Problems to be Solved by the Invention) The TPT matrix array panel having the above-described structure and manufacturing method has a disadvantage in that display line defects due to wire breakage are likely to occur due to the structure. These drawbacks are due to the fact that the semiconductor film is separated and insulated in a plane due to the structure in which the TPTs are provided in a matrix array.

In general, in liquid crystal display devices, active materials)
In many cases, an IJ Waxley panel is made to have a light-transmitting property, and not only in the case of the above-mentioned TPT, unnecessary regions of a semiconductor film with poor light-transmitting properties must be removed by etching. Furthermore, even in the case of a reflective liquid crystal display device that does not have light transmission properties, an etching process is required to separate the elements in order to prevent crosstalk between active elements as much as possible.

Furthermore, the semiconductor a is generally not required and no semiconductor film is provided in the lead wiring and terminal portions in areas where active elements are not provided. For this reason, a large step is formed at the end of the semiconductor film, which has the disadvantage that wiring to the terminal portion that crosses this step is easily disconnected.

As the display capacity increases, the number of wiring increases, and
A display device with 0.00 x 640 pixels has 1040 wires, which is a severe problem in which even a 0.1% disconnection probability cannot be tolerated.

In devices where wiring breaks occur, they appear as line defects in the display, resulting in a significant deterioration in display quality. For this reason, there is a problem in that extra steps are required, such as plating the metal for the upper wiring to make it thicker in a separate step to repair the sag, and reconnecting broken wires.

(Object of the Invention) Therefore, an object of the present invention is to provide an active matrix array panel and a method of manufacturing the same, which requires fewer manufacturing steps and has an excellent manufacturing yield.

According to the first invention of the present application, a plurality of scanning lines and signal lines are insulated from each other and provided in a matrix array on an insulating substrate, and the scanning lines In a panel in which a switching element is provided in the vicinity of an intersection between a signal line and a signal line, the semiconductor thin film used for the switching element is connected to the signal line (or scanning, 11) which becomes an upper electrode of the switching element.
An active matrix array panel is obtained which is characterized in that the active matrix array panel is provided in all areas under the wiring and terminals.

Further, according to the second invention of the present application, in the manufacturing method in which a plurality of scanning lines and signal lines are provided in a matrix array on an insulating substrate via a semiconductor thin film, the signal 1ll (or forming the semiconductor thin film over an area including the wiring area of the scanning line (scanning line) and the terminal area; and removing the desired area of the semiconductor thin film at the same time as patterning the wiring and terminal of the signal line (or scanning line). A manufacturing method is obtained, which is characterized in that it includes the steps of:

(Function) In the active matrix array panel of the present invention, the semiconductor film is provided in all areas under the wiring and terminals of the signal line (scanning II) serving as the upper electrode of the switching element by the above means. Since the number and height of steps between the electrode wiring and the terminal portion can be significantly reduced, and the adhesion of the wiring is also improved, the probability of wire breakage occurring can be significantly reduced.

Therefore, as an industrial advantage, the occurrence of line defects in display devices can be suppressed, and yields can be extremely improved. Further, there is no need to add a separate process for repairing the disconnection, and costs can be reduced.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

(Example 1) Figure 1 shows a T to which the configuration of the embodiment of the first invention of the present application is applied.
They are a schematic plan view (b) of a part of an FT matrix and a Kusaray panel, and a schematic cross-sectional view (a) taken along a line AA'.

In FIG. 1, a gate electrode 102 made of Cr is patterned and provided on an insulating substrate 101 of soda glass coated with 870.

On top of this, a gate insulating film 103 of SiN formed using plasma CVD and a semiconductor film 104 of a-3i:[ from the i layer and the n2 semiconductor layer 105 are provided. Furthermore, a drain electrode 108 is placed on top of this. A Cr wiring metal 106 for the source electrode 110 is provided. The Cr wiring metal 106 is located in the region 113 where the semiconductor M104 is provided.
As a result, the drain electrode ios s, the drain pass line 116 part, and the terminal electrode IQ9 part have the same laminated film structure, and these have the same structure as the gate insulator 1103. (Considered as a semiconductor film in a broad sense, it is provided by laminating a semiconductor M 104, an n'' semiconductor layer 105, a wiring metal 106, and an ITO film 107.

The semiconductor film other than the semiconductor region 113 (indicated by dots in the figure) including the region that will become the TFT 112 and the drain electrode wiring region is etched away.

An ITO film 1 is formed on the Cr wiring metal 106 and the SiN gate insulating film 103 remaining in the region that will become the display electrode 1i1.
07 is provided to form a desired pattern. The pattern of the ITO film 107 is such that the display electrode 111 and Tl
The source electrode 110 of the TFT 112 is connected, the drain electrode 108 and the drain terminal electrode 109 are continuous, and there is a gap between the source electrode 110 and the drain electrode 108 in the channel part of the TFT 112.
In the channel portion of the TFT 112, the ITO film 107, the Cr wiring gold II&106, and the n+ semiconductor layer 105 are removed, leaving the semiconductor film 104 with the i-layer exposed.

As a result of measuring the individual TFT % properties of the TPT matrix array panel of the present application having the structure as described above,
It was confirmed that there was no influence between the TFTs in the IJ sock, and that the TPT could be operated for each display electrode. This is the switching operation of TPT.

Looking at the positional relationship between the gate electrode and TPT for
The effect was that the TPT on the gate electrode wiring was separated by the semiconductor film, and the TPT on the drain electrode wiring had an independent gate electrode. In addition, the display results of a liquid crystal display using this TPT matrix array panel are as follows:
r) It was exactly the same as the isolation isolation method in the shape of a Q box. This is done by sequentially inputting a display timing signal to each gate line in a liquid crystal display for switching.

Because it is a so-called line-sequential method, there is no TI” in the drain direction.
Even if T is provided in common, the switching timing is different, which is an effect that causes no problems at all.

Furthermore, there is only a slight step in the thickness of the gate electrode in the continuous wiring between the drain electrode, drain pass line, and terminal electrode, and there is no step due to insulation separation of TPT or the edge of plasma CVD film formation, so there is no disconnection due to the step. We were able to create panels with no blemishes at an extremely high yield. As a result, we were able to eliminate a separate process for repairing broken wires. Therefore, even though it is desired to reduce the number of steps, when a liquid crystal display panel is manufactured, there are no line defects and the display quality is improved.

(Example 2) Figure 1s2 is a schematic cross-sectional view of a part of a TPT matrix array panel in the manufacturing process of the panel in which the method of the example of the second invention of the present application is applied, and Figure 3 is a schematic cross-sectional view of a part of the panel in that process. It is a schematic plan view of a part of. In Figs. 2 and 3, (al~(φ are opposite, ls2
The figure illustrates a cross section taken along the line AA' in FIG. 3.

[In Figures 2 and 3, an insulating substrate 20 such as glass
1 on top of Cr%1000A for gate electrode 202.302
Deposition and patterning [process ((萄)].

After that, the gate insulating film 20 is formed using plasma CVD.
300 OA of S2N for semiconductor film 204 was deposited, and 113,000 OA of a-8i:H for semiconductor film 204 and n? 50% of phosphorus-doped a-8i:H skin on the semiconductor shoulder
Deposit 0A [Process manual]. These plasma CvD
The film forming region of the semiconductor film using the above includes a region where an active matrix is provided and a drain terminal region, excluding the gate terminal region, and the film forming end 214.314 is close to the glass end 200.300.

Next, in a separate process subsequent to this surface, 200 OA of Cr is deposited to become the wiring metal 206 and 306 for the drain electrode.

A wiring metal 206, as shown in FIG. 3(C), includes a TPT region in which the drain electrode wiring and the drain electrode terminal are continuous, and the drain electrode and the source electrode are continuous.
Cr is etched using a mask pattern 306 (shaded area). The n9 (semiconductor) layer 205 of the a-8i:H film of the semiconductor film 204 was deposited by plasma CVD [step (b)] using the same mask pattern. 305 and the i-layer are removed by etching [Step (C)]. As a result, a of the stacked deposition region 314 of the gate insulating film, semiconductor film, and n layer deposited by plasma CVD (step (b)) is
The semiconductor region 311 in which the -Si:H film (n layer + i layer) remains is the same as the Cr wiring metal 306, and is shown in FIG.
This is the shaded area in C). Next, a display electrode 31 is placed on this surface.
1 as an ITO film 207. 307 is deposited to form a pattern as shown in FIG. Etch the ITO film 207 and 307 using a separate material.Subsequently, using the same mass sound, etching the Cr film of the wiring metal 306 existing in the channel portion of the TFT 312 and the a-84 of the n+ (semiconductor) layer 305 of the semiconductor ffl 304: Unnecessary M such as Hn''1 is removed by etching [Step (d)]. Among these etching types, the etchant for ITO, the etchant for Or, and the etchant for a-8i:HJ or their etching gases are not suitable for S:N. Since the selectivity is sufficient for the gate insulator 303, it remains in the entire region deposited by plasma CVD.In addition, in the TFT 312 region, the channel part is a semiconductor [a-8i:H film i layer of 304 is exposed. I'm here.

In addition, in step (d), the glass edge 200.30
In some cases, the edge of the glass substrate is cut off at the same time as the liquid crystal display panel is assembled, in order to remove distortions and the like that remain at zero. In that case, the new glass edge 218.degree. 318 and the edge of the terminal electrode 209.309 coincide.

As described above, in the case of this embodiment, the basic example includes the patterning process (a) of the gate electrode, the patterning process (C) in which the drain electrode and TPT are integrated, and the patterning of the display electrode and TPT channel. The masking step (d) requires only three masking steps, and the mask for the conventional TPT matrix separation technique is not required, resulting in a significant reduction in the number of man-hours and manufacturing costs.

Furthermore, although ITO [on the drain electrode] is inherently unstable, if the above mask is used, the ITO [on the drain electrode 2
08.308 and drain terminal electrode 209°309 are n
It is composed of three layers: a-8i film, Cr film, and ITO3 film, and contributes to lower wiring resistance and fewer disconnections.

Further, although the semiconductor film is essentially unnecessary except in the region where the active element is provided, the present invention achieves the following object by providing the semiconductor film.

Drain electrode 2Q8. 308 and drain pass line 2
Since the gate insulating film 203.303 (semiconductor film in a broad sense) and the semiconductor film 204.304 are left in a stacked state under each of 16 and 316 and the terminal electrode 2Q9.3Q9, one child from the drain electrode Until then, there were fewer steps and fewer steps in the wiring, and the causes of wire breakage were significantly reduced.

In addition, compared to the conventional case where the terminal portion and drain path line drawer are on a-bx glass substrates, for example, even in the case of aluminum wiring, the adhesive strength to the semiconductor film is superior to the adhesive strength to glass, and the wiring is not disconnected due to peeling. Although the active matrix array panel of the HAiTFT developed in the present invention has been described above, it can be implemented in the same manner with a diode panel using a thin film semiconductor. TPT
In this case, it has a staggered electrode structure, and the gate or source/drain electrodes serve as upper electrodes with a thin film semiconductor sandwiched between them. On the other hand, since the diode has a sandwich electrode structure, the upper electrode sandwiching the thin film semiconductor serves as one side electrode of the diode. The present invention uses a structure and method in which a semiconductor thin film is provided on the bottom electrode wiring from the upper electrode of these active elements to the lead-out terminal to reduce the level difference and eliminate defects due to disconnection. In addition, the upper part has a structure in which the electrode wiring metal is entirely on the semiconductor thin film up to the terminal electrode part,
Since it is a method, the adhesion of the wiring metal is high, and disconnection defects due to peeling can be eliminated. When the present invention is applied to a matrix array panel of coplanar active elements, the structure and method may be such that a semiconductor film is provided on the wiring bottom from the wiring electrode to the terminal portion.

(Effect of the invention) As explained in detail above, the active material of the present invention)
In the IJ Fuchsley panel and its manufacturing method, the active element! Among the poles, we have adopted a structure and method in which the electrode that serves as the upper electrode for the semiconductor thin film and all the partial pressure semiconductor thin films from its wiring to the lead terminal are provided, which not only reduces the masking process but also eliminates the need for steps due to wiring steps. It is possible to significantly reduce wire breaks due to wire breakage and peeling, thereby reducing manufacturing costs and improving manufacturing yield.

Therefore, when the active matrix array panel of the present invention is used in a liquid crystal display panel, a display with high image quality and no line defects can be obtained.

Another advantage is that there is no need for a separate fence to repair broken wires.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a part of an embodiment of the first invention of the present application (mill) and a schematic cross-sectional view taken along the A-A' break line (a
), FIG. 2 is a schematic sectional view of a part of the panel in the manufacturing process showing the method of an embodiment of the second invention of the present application, and FIG.
The figure is a schematic plan view of a part of the panel in the process shown relative to Figure 1J2, and (a) of Figures 2 and 3.
~(Φ is a diagram explaining the process order, FIG. 4 is a schematic plan view of a part of the panel (fat is a schematic cross-sectional view seen from the BL and A-A' break lines) In the figure, 101, 201.401 are insulating substrates, 200.3
00 is the glass edge, 102.202.3Q2.402 is the gate electrode, 103°203, 303.493 is the gate insulating film, 104.204°304, 404 is the semiconductor film, 1
05.205.305.405 is n+ semiconductor layer, 1
06.206.306.406 H wiring metal, 107.
207.307.407 is an ITO film, 108.208°308, 408 is a drain electrode, 109.209.30
9°409 is a terminal electrode, 110.310.410 is a source electrode, 111, 311.411 is a display electrode, 11
2,312,412 FiTFT, 113,31
3,413 is semiconductor film area% 214°314.414
is the film forming edge, 415Vi etching residue, 116°216,
316.416 indicates a drain pass line, 317 indicates a cutting line of the glass substrate, and 218.318Fi indicates a new glass substrate end. ←

Claims (1)

[Claims] 1. A plurality of scanning lines and signal lines are provided in a matrix array on an insulating substrate, and are insulated from each other, and a switching element is provided near the intersection of the scanning lines and the signal lines. In the provided panel, the semiconductor thin film used for the switching element is provided in all areas under the wiring and terminals of the signal line (or scanning line) that becomes the upper electrode of the switching element. active matrix array panel. 2. In a manufacturing method in which a plurality of scanning lines and signal lines are provided in a matrix array on an insulating substrate via a semiconductor thin film, the wiring area and terminal of the signal line (or scanning line) provided on the semiconductor thin film. and a step of removing unnecessary regions of the semiconductor thin film at the same time as patterning the wiring and terminals of the signal lines (or scanning lines). A method for manufacturing an active matrix array panel.