JPS622348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, in particular, a master device having an information processing function and a plurality of slave devices controlled by the master device are connected in parallel via a common bus. This paper relates to a synchronization method in a bus system.

Generally, this type of bus system is divided into an asynchronous system that does not use a bus clock and a synchronous system that uses a bus clock.

Figures 1A to 1C are explanatory diagrams for explaining the asynchronous system, Figures 2A to 2C are explanatory diagrams for explaining the synchronous system, and Figures 1A and 2A are block diagrams showing the configuration of the bus system, respectively. Figures 1B and 2B are circuit diagrams showing the interface section of the slave device, and Figures 1C and 2C are the circuit diagrams showing the interface section of the slave device, respectively.
It is a time chart explaining the operation of figures B and 2B.

First, the asynchronous method will be explained.

As is clear from FIG. 1A, the master device 1 and slave device 2 are connected to the common bus 3.
connected via. Data bus 3 is address bus (ADRESS/BUS), data bus (DATA/BUS), and write operation signal ()
It consists of a line, a read operation signal ( ) line, a bus busy signal ( ) line, a data capture completion signal ( ) line, etc. Note that the (-) mark attached to each signal indicates that the signal is active when it is at a "low" level. Also, although the figure only shows one master device and one slave device,
A plurality of each can be provided.

As shown in FIG. 1B, the slave device includes a data register (DRG) 4, a delay circuit 5, AND gates AN1, AN2, and an inverter IN1,
Consists of IN2 etc.

Here, the operation in which the master device 1 transfers data to the slave device 2 (Date Write) will be explained with particular reference to FIGS. 1B and 1C.

First, when the master device acquires the right to use the bus by a bus priority control circuit (not shown), the first
Set the bus busy signal () to “low” as shown in Figure C.
level. The master device then selects the first C
As shown in Figures C and B, when the write operation signal () is set to “low” level, the data (DATA) is
Output. When the slave device shown in FIG. 1B receives the write operation signal (), the delay circuit 5 takes a predetermined skew time _T0 as shown in FIG. When the data acquisition is completed, a data acquisition completion signal ( ) is returned as shown in FIG. 1C.

In this way, in the asynchronous method, the delay circuit 5 for ensuring the skew time T ₀ , the differentiating circuit (configured by the delay circuit 5, the inverter IN1, and the AND gate AN1) that generates a pulse for loading data into the register 4 are used. ), which has the disadvantage of making the circuit extremely complicated.

Next, the synchronization method will be explained.

As is clear from FIG. 2A, the feature of this system is that a device for supplying a clock to the common bus 3, that is, a bus controller (BSC) 6 is provided. Therefore, all the signals on the bus can be synchronized to the bus clock ( ) as shown in Figure 2C, so that the slave device can also be configured with a flip-flop circuit 7 and simple gate circuits AN, IN as shown in Figure 2B. It can be configured by Further, as shown by the solid arrow in FIG. 2C, the above-mentioned skew time can be easily taken by the bus clock ().

However, the synchronous method has the disadvantage that a separate bus controller is required to supply the above-mentioned clock signal.

Incidentally, a master device generally has an information processing function, and therefore usually has its own internal clock source. Since this internal clock is unrelated to the bus clock, a separate circuit is required to synchronize the internal clock with the bus clock.

FIG. 3 is a circuit diagram showing an example of an interface circuit of a master device when a synchronous method is adopted.

In the figure, 8 is a processor, 9 is a bus priority control circuit, 10 is an interface section, and FF1 to FF.
8 is a flip-flop, DR is a driver, and 3 is a common bus.

Here, a case will be described in which a master device transfers data to a slave device having a predetermined address. In this case, the master device processor 8 first sends a bus use request signal (REQ) to the bus priority control circuit 9. The bus priority control circuit 9 determines the priority of the master device, and when it has the highest priority, sends a bus use permission signal (PMT) to each driver DR of the interface circuit 10 via the flip-flop FF2. At this time, the bus clock signal ( ) is applied to the clock terminal of flip-flop FF2, and the clock terminal of flip-flop FF3 to FF
7 is provided with an internal clock (iCLK), which provides synchronization.
In this way, the address signal (ADDRESS) and data (DATA) from the processor 8 are applied to a desired slave device via the flip-flops FF3 and FF5, the address bus, and the data bus.

That is, it has the disadvantage that a complicated circuit as described above is required in order to synchronize the clock of the master device and the bus clock.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a bus system that can operate in a synchronous manner without providing a special device for supplying clock signals.

Its features include using the master device's original clock source as a synchronous clock;
By controlling how the clock is applied, the slave device can recover using the clock, thereby achieving synchronization without requiring a special clock source.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4A is a block diagram showing an embodiment of the present invention, and FIG. 4B is an operation waveform diagram for explaining its operation.

In FIG. 4A, 11 is a clock delay circuit especially added according to the present invention, AN is an AND gate, OR is an OR gate, DR is a driver, IN is an inverter, FF9 and FF10 are flip-flops, and 8
9 is a processor similar to that shown in FIG. 3, and 9 is a bus priority control circuit.

The operation will be explained with reference also to FIG. 4B.

When a master device 1 consisting of a processor 8, a bus priority control circuit 9, a clock delay circuit 11, etc. sends a bus request signal (REQ) from the processor 8 to communicate with a slave device (not shown), the bus priority control circuit 9 checks the bus request signals (BRQ ₁ to n) from other master devices to determine the priority of the master device, and if it has the highest priority, outputs the signal PSG to one terminal of the AND gate AN. do. Here, if bus 3 is not in use, the signal is at a high level, and this signal is applied to the other terminal of AND gate AN, so AND gate AN is opened, flip-flop FF9 is set, and the internal bus signal is () is sent. As a result, bus 3 becomes busy (low level) as shown in Figure 4B (b), while the OR gate
Since the driver DR is driven via the OR, the clock signal ( ) from the processor 8 as shown in FIG. 4B is sent out as the bus clock signal ( ) of the common bus 3 as shown in FIG. At this time, flip-flop FF10 is connected to inverter IN.
is set via , but is not directly related to the above operation. From then on, predetermined communications are performed in this state, but when the communications are completed and the bus in use signal () becomes high level as shown in Figure 4 (b),
AND gate AN is closed and the signal becomes high level. As a result, the bus busy signal () also goes high and indicates "vacant", while the flip-flop 10 is reset.
In this case, if the flip-flop 10 outputs the input signal at the rising edge of the next clock ( ), a one-clock delay can be created as shown in FIG. By setting the output to a low level, the driver DR is opened via the OR gate, and a one-cycle clock signal () is sent out. Upon receiving this one-cycle clock signal, the slave device side detects that the bus busy signal () is at a high level, that is, has been erased, and performs its own recovery operation. That is, the clock extension circuit is provided to secure time for self-recovery of the slave device by sending out a clock signal for at least one cycle after a predetermined operation is completed.

As described above, according to the present invention, since the bus clock is supplied from the master device that uses the common bus, synchronization can be performed using a simple circuit without providing a special bus clock generator as shown in FIG. 2A. It is possible to realize data transfer according to the method. Furthermore, when multiple master devices are provided, each master device supplies its own clock as the bus clock, so even if one master device becomes inoperable, the function of that master device will only be lost. ,
It does not affect other master devices in any way. Furthermore, when another master device is using the bus, the bus busy signal (BSY) becomes active (low level), so even if the bus request signal (REQ) is issued, the bus priority control circuit Since the use permission signal (PSG) is not issued, the internal bus signal (iBSY) is also not issued, which means that the bus clock is always supplied from only one master device, and there is no possibility of two clocks competing with each other.

[Brief explanation of the drawing]

Figure 1A is a block diagram showing the configuration of a general asynchronous bus system, Figure 1B is a circuit diagram showing the interface section of a slave device, and Figure 1C is a block diagram showing the configuration of a general asynchronous bus system.
The figures are a time chart for explaining the operation of Fig. 1B, Fig. 2A is a block diagram showing the configuration of a general synchronous bus system, Fig. 2B is a circuit diagram showing the interface section of the slave device, and Fig. 2C
The figures are a time chart for explaining the operation of Fig. 2B, Fig. 3 is a circuit diagram showing the interface section of the master device when the synchronization method is adopted, and Fig. 4 is a time chart for explaining the operation of Fig. 2B.
Figure A is a block diagram showing an embodiment of this invention.
Figure B is an operation waveform diagram for explaining the operation. Description of symbols, 1...Master device, 2...Slave device, 3...Common bus, 4...Data register, 5...Delay circuit, 6...Bus controller, 7, FF1 to FF10...Flip-flop,
8...Processor, 9...Bus priority control circuit, 1
0...Interface section, 11...Clock extension circuit, AN, AN1, AN2...And gate,
IN, IN1, IN2...Inverter.

Claims (1)

[Claims] 1. At least one master device equipped with a clock signal source and having an information processing function and a plurality of slave devices controlled by the master device are connected in parallel to each other via a common bus,
When the master device acquires the right to use the bus, it sends out a bus-in-use signal and synchronizes the master device and slave device with each other by supplying a clock signal from the master device as a synchronization signal. A bus system for exchanging signals or information,
The master device extends the clock signal by at least one cycle even after the end of the bus busy signal, so that the slave device can detect the disappearance of the bus busy signal and shift to a recovery operation. A bus system characterized by securing the necessary time.