JPS6225219B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage element, and more particularly to a storage element capable of collecting stored fault information.

In general, the degree of integration of memory elements has increased with the advancement of technology, and in order to collect data in the event of a failure in a data processing device that uses memory elements, the address of the memory element is given externally, and the output is received by a register or the like. A method has been adopted in which the contents of a register are collected as fault information, and it is considered that a scan path can be used as a means of providing an address at this time.

A conventional memory element will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram including an example of a conventional device, in which an address register B is connected to a storage element A, and an address input signal 50 is supplied to address input terminals S0 to S9.

This address input signal 50 is supplied to the address decoder 2 and drives the memory array 1. At the time of writing/reading of memory array 1, enable signal 55 is supplied to enable terminals E0 to E2, and enable signal 58 is generated via AND gate 5.

When writing to the memory array 1, the write enable signal 56 is supplied to the write enable terminal WE, and the write instruction signal 5 is sent via the driver 10.
9, and the data input terminal OA
A data input signal 54 is generated. permission signal 58
Since both the and write instruction signal 59 are generated, the read permission signal 63 is not output from the AND gate 8, but the write permission signal 60 is output from the AND gate 7. A write data signal 61 is generated.

As a result, memory array 1 is instructed to write to the address driven by address decoder 2 by write instruction signal 59, and write data signal 61 is written.

When reading the memory array 1, the write enable signal 56 is not supplied, so the enable terminal E
When enable signal 55 is supplied to 0 to E2, AND gate 7 does not output write instruction signal 60, and AND gate 8 generates read instruction signal 63.

As a result, a read data signal 62 read from the memory array 1 from the address driven by the address decoder 2 is outputted as an output data signal 64 by the NAND gate 9 and outputted to the data output terminal F0.

In the address register B mentioned above, addresses are set or counted up in parallel during normal operations such as reading and writing.

However, when a failure occurs, this address register B is also subject to testing, so it is necessary to set an address in address register B without using means for setting addresses in parallel or means for counting up.

For this reason, address register B is used as a component in the scan path, and each time a clock is supplied to it, an address is shifted in and set one bit at a time.

Therefore, in the memory element shown in FIG. 1, in order to read one memory location, the address input signal 50 is
As a result, 10 bits must be shifted in, which takes 10 clocks.

Moreover, it is clear that reading fault information from a large number of storage locations requires even more time.

That is, the conventional memory element has the disadvantage that it takes a lot of time to provide an address and that it is necessary to have a separate means for updating the address.

An object of the present invention is to provide a memory element that can speed up collection of fault information.

That is, an object of the present invention is to provide a counter for providing an address inside a storage element and to provide a means for updating the address in order to collect failure information, etc. by providing a counter for giving an address from the outside, and a means for updating the address in order to collect failure information, etc., and a method for scanning the address information. It is an object of the present invention to provide a memory element that can be used and saves time.

The storage element of the present invention includes a memory array in which fault information is stored, a counter that counts and outputs a counter output signal by supplying a count-up instruction signal, and an address register by a switching instruction signal supplied when collecting fault information. The memory array includes a selector that switches an address input signal from the counter to the counter output signal and outputs it as an access address signal, and an address decoder that drives the memory array in accordance with the access address signal.

That is, the memory element of the present invention includes a memory array, means for instructing an address for writing to or reading from the memory array from an address register, means for externally providing write data and write timing, and a means for providing write data and write timing from the outside. a writable and readable storage element having means for outputting stored data to the outside, means for giving an instruction to sequentially read failure information stored in the memory array; and a counter for giving an address of the memory array during the read instruction; means for clearing the counter; means for setting the output of the counter as an address of the memory array during the read instruction; and means for setting the address from the address register as the address of the memory array when there is no read instruction; and updating means.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block circuit diagram containing one embodiment of the present invention.

The memory element A′ shown in FIG. 2 is the memory array 1,
Address decoder and driver 2, selector 3, counter 4, and gate 5, 6, 7, 8,
It includes a NAND gate 9, a driver 10, a plurality of address input signals 50, a switching instruction signal 51, a counter clear signal 52, a count up instruction signal 53, a data input signal 54, an enable signal 55, a write enable signal 56, and an output data signal 64. configured.

Below, the functional operation of the present invention will be explained in detail with reference to FIG.

When sequentially collecting the fault information stored in the memory element, first, the switching instruction terminal is
By supplying the switching instruction signal 51 to the SW, the selector 3 inputs the address register B from the address input terminals S0 to
Counter output signal 57 supplied from counter 4 instead of address input signal 50 supplied to S9
is selected and output as the access address signal 65. Next, the counter clear signal 52 is supplied to the count clear terminal MR to clear the counter 4. As a result, the counter output signals 57 all become "0" and are inputted to the memory array 1 via the selector 3, the address decoder 2, and the address decoder 2. Data at address=0 is output as a read data signal 62, passes through the NAND gate 9, and is output as an output data signal 64 to the data output terminal F0. This output data signal 64 can be sampled by a conventional method such as receiving it in a register or the like.

After data at address=0 is collected, a count-up signal 53 is supplied to update the counter 4, and data at address=1 is collected next.

Data is collected by counting up this as many times as necessary and repeating data collection.

That is, the memory element of the present invention supplies a switching instruction signal when collecting failure information, and only needs to supply one bit as a count-up instruction signal to obtain an address. requires only one clock, which speeds up address updating.

By adding a counter and a selector to the memory element of the present invention, the output of the counter can be set in parallel as an address instead of serially shifting in the address supplied when collecting fault information one bit at a time. This has the effect of speeding up the collection of fault information because the setup time can be shortened.

That is, the storage device of the present invention uses a scan path to collect storage information when a failure occurs by adding a selector and a counter.
Instead of scanning in one bit each clock to set the required number of bits in the address, you can select addresses from a counter that counts up each clock and set them in parallel.
This has the effect of shortening the time required to collect memory information.

That is, the memory element of the present invention is configured to have a counter internally providing an address and a means for switching with an address instruction from the outside and instructing an update of the counter, thereby eliminating the need for a means for updating the address and improving storage efficiency. This has the advantage that information within the element can be collected in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram including an example of a conventional memory element, and FIG. 2 is a block circuit diagram including an embodiment of the present invention. A, A'...Storage element, B...Address register, 1...Memory array, 2...Address decoder, 3...Selector, 4...Counter, 5, 6,
7, 8...and gate, 9...nand gate,
10...Driver, S0-S9...Address input terminal, OA...Data input terminal, E0-E2...
Enable terminal, WE...Write enable terminal, F0...Data output terminal, SW...Switching instruction terminal, MR...Count clear terminal, CU...Count up terminal, 50...Address input signal,
51...Switching instruction signal, 52...Counter clear signal, 53...Count up instruction signal, 54...
...Data input signal, 55...Enable signal, 5
6...Write enable signal, 57...Counter output signal, 58...Permit signal, 59...Write instruction signal, 60...Write permission signal, 61...Write data signal, 62...Read data signal , 63...read permission signal, 64...output data signal, 65...access address signal.

Claims (1)

[Claims] 1 A memory array in which fault information is stored, a counter that counts and outputs a counter output signal by supplying a count-up instruction signal, and an address input signal from an address register by a switching instruction signal supplied when collecting fault information. A memory element comprising: a selector that switches to the counter output signal and outputs it as an access address signal; and an address decoder that drives the memory array in accordance with the access address signal.