JPS6225254B2 - - Google Patents
Info
- Publication number
- JPS6225254B2 JPS6225254B2 JP5647377A JP5647377A JPS6225254B2 JP S6225254 B2 JPS6225254 B2 JP S6225254B2 JP 5647377 A JP5647377 A JP 5647377A JP 5647377 A JP5647377 A JP 5647377A JP S6225254 B2 JPS6225254 B2 JP S6225254B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- reaction
- reaction vessel
- gas
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 36
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 12
- 238000010574 gas phase reaction Methods 0.000 claims description 8
- 239000012495 reaction gas Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000010453 quartz Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000012808 vapor phase Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000012071 phase Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
Landscapes
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
Description
【発明の詳細な説明】
本発明は半導体基板の気相反応装置にかゝり、
特に半導体基板に気相反応を施すための改良され
た構造の気相反応装置を提供するものである。
一例の半導体装置の製造において、半導体基板
に気相における反応を施し、その表面に酸化膜形
成、領域形成のための不純物拡散導入等を施す工
程があり、これに用いられる装置を半導体基板の
気相反応装置と称せられている。第1図に示すモ
ス型電界効果半導体装置(以降MOS―FETと記
す)の一部を示す断面図において、1は比抵抗値
が1〜10ΩcmのN型シリコン基板、2はソース領
域3はドレイン領域でともに前記基板の1主面に
形成されたSiO2層4をマスクとしてP型不純物
を選択的に拡散導入して形成される。また12は
ソース領域2の露出面に設けられたソース電極、
13はドレイン領域3の露出面に設けられたドレ
イン電極、15はゲート電極で、前記ソース領域
およびドレイン領域の間の基板主面上にゲート酸
化膜5を介して形成される。そして動作により空
乏層、反転層が形成されるところであるが、シリ
コン基板とこれに接触したSiO2層との界面は非
常に複雑な様相を呈し、Si―SiO2界面は金属(電
極)―酸化物―半導体間の仕事関数差(φMS)に
よる電荷の誘起、酸化物と半導体との結晶構造差
による不連続から生ずる結晶不整、高温酸化中に
酸化された部分に存在した不純物や、O2のSi中
への拡散などで正常でなくなる。さらには処理工
程でSiO2に不本意に付着していて侵入する不純
物による汚染は表面欠陥層、SiO2中に荷電体と
して存在し、Si表面の電子状態に大きな影響を与
え、ひいてはFETの安定性に問題をおよぼす。
上記の理由にもとづき、製造工程においてはその
取扱いに周到な注意を要し、上記MOS―FET、
さらにはMOS―IC等の製造における酸化層形
成、不純物拡散等の気相成長が一般には不所望の
不純物混入、耐熱性などの面から反応容器として
特に高純度の石英管が用いられている。そして第
2図に示す如く、石英管6の一端に反応の雰囲気
を形成するためのガス導入部(一部のガス導入管
7の一部を除き、ガス源、ガス量調整装置等の記
載を省略して示す)7を備え、他端は開放にて
こゝから半導体基板8を支持した半導体基板支持
治具18を装入する。この装入には第3図に示す
如く半導体基板支持治具移動用棒体9(以降移動
用棒体と略称する)を用いて行なう。なお上記移
動用棒体は半導体基板支持治具の取り出しにも用
いうる如く先端部に「かぎ部」9aが形成され
る。
上記半導体基板は石英管に外囲する高周波コイ
ルに通電し、均熱管によつて加熱されて所定の雰
囲気にて気相反応が施される。そして反応が完了
し降温段階に移ると、第3図に示す如く移動用棒
体を挿入して操作(取り出し)するが、容器内に
外気(空気)が対流によつて流入する。
上記により半導体基板に反(そ)りとQss
(Surface State)の増大が発生する。上記反りは
一例として写真蝕刻の際のマスクの圧着不良によ
りパターンの精度を低下し、微細パターニングを
損ずるという欠点がある。またQssの増大は半導
体基板に形成される一例のSiO2層の層質を低下
せしめるという重大な欠点がある。(なお上記
Qssは界面系に介在する実効的な全電荷を示し、
次式
Qss=Vss×Cox
にて表わされる。たゞし上式におけるCoxは酸化
膜の電荷容量、Vss≡Vth−V1thにてVthは「し
きい値(スレシヨルド)電圧」、V1thは「真性し
きい値電圧」を表わすものとする。)
本発明は上記従来の気相反応装置における欠点
を除去するための改良された半導体基板の気相反
応装置を提供するものである。
この発明にかかる半導体基板の気相反応装置
は、一端にガス排出口を有し他端がふた体にて閉
塞される耐熱性の気相反応容器、前記反応容器を
取囲む加熱手段、前記反応容器内に半導体基板支
持治具に載置された半導体基板に気相反応を施す
ための反応ガスを導入する反応ガス導入部を具備
した半導体基板反相装置において、ふた体が、平
面部と、この平面部の周縁ににてこの平面部から
延在された側面部を有し、かつこの側面部は少く
とも一部が反応容器の開端と遊嵌し、これを閉塞
するとともに、平面部に設けられた半導体基板支
持治具を通過させる開孔とこれを側面部に延長し
た切抜部を有することを特徴とするものである。
次に本発明を一実施例の半導体基板の気相反応
装置につき図面を参照して詳細に説明する。側面
断面図で示す第4図において、6は反応容器の石
英管で、その一端に反応の雰囲気を形成するため
のガス導入部7(一部のガス導入管の一部を除
き、ガス源、ガス量調整装置等の記載を省略して
示す)を備え、他の一端は開放にてこゝから半導
体基板8を支持した半導体基板支持治具18を装
入する。この装入には第6図ないし第7図に示す
如き移動用棒体9を用いて行なう。なお上記移動
用棒体は半導体基板支持治具の取り出しにも用い
うる如くその先端部に「かぎ部」が形成される。
上記半導体基板は石英管に外囲する高周波コイル
に通電し、均熱管によつて加熱され、所定の雰囲
気にて気相反応が施される。そして反応が完了し
たとき第4図および第5図に示す如きふた体10
を石英管6の開放端部に装着する。上記ふた体は
前記石英管6と同じ材質の石英でなり、第5図a
に軸線方向から視た側面図、図bに側面断面図、
図cに下面図で示す如く、開孔10c′を有する平
面部10a(図a)と、この平面部の周縁から垂
直に延在した側面部10b(図b)を備え、この
側面部の端部にて石英管6の側面に遊嵌し着脱自
在になる。また、上記開孔10c′はこれが側面部
10bに延長されて切抜部10cを形成する。
本発明によれば反応容器内に外気の対流流入が
防止されるので、半導体基板の反(そ)りとQss
の増大が防止できる顕著な利点がある。すなわち
反りは一例の写真蝕刻の際のマスクの圧接不良に
よるパターン精度の低下をきたし、微細パターニ
ングが損せられる。またQssの増大はMOS―
FET、MOS―ICの電気的特性を損ずる。本発明
は一例のMOS ICにおけるVth値のバラツキを従
来の±0.36vから±0.12vに低減をみた。次に本発
明にかゝるふた体の形状によれば、第6図に示す
如く気相反応容器の石英管端部に被嵌せしめた場
合、移動用棒体9の挿入が容易であり、また第7
図に示す如く棒体を上下させる角度(θ)が広く
許容できるので、反応容器の設置高さが移動用棒
体の操作者の高さと相当に相違してもこの棒体を
折損することなく操作が容易に達成できるなどの
利点がある。 DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vapor phase reaction device for a semiconductor substrate.
In particular, it is an object of the present invention to provide a gas phase reactor having an improved structure for performing a gas phase reaction on a semiconductor substrate. For example, in the manufacture of semiconductor devices, there is a process in which a semiconductor substrate is subjected to a reaction in the gas phase to form an oxide film on its surface and to diffuse impurities to form regions. It is called a phase reactor. In the cross-sectional view showing a part of the MOS-type field effect semiconductor device (hereinafter referred to as MOS-FET) shown in Fig. 1, 1 is an N-type silicon substrate with a specific resistance value of 1 to 10 Ωcm, 2 is a source region 3 is a drain Both regions are formed by selectively diffusing and introducing P-type impurities using the SiO 2 layer 4 formed on one main surface of the substrate as a mask. Further, 12 is a source electrode provided on the exposed surface of the source region 2;
A drain electrode 13 is provided on the exposed surface of the drain region 3, and a gate electrode 15 is formed on the main surface of the substrate between the source region and the drain region with the gate oxide film 5 interposed therebetween. A depletion layer and an inversion layer are formed by the operation, but the interface between the silicon substrate and the SiO 2 layer in contact with it has a very complicated appearance, and the Si-SiO 2 interface is a metal (electrode)-oxidation layer. Induction of charge due to the work function difference (φ MS ) between a substance and a semiconductor, crystal irregularity caused by discontinuity due to a difference in crystal structure between an oxide and a semiconductor, impurities present in the oxidized part during high-temperature oxidation, and O 2 becomes abnormal due to diffusion into Si. Furthermore, contamination caused by impurities that are inadvertently attached to SiO 2 and enter during the processing process exists as a surface defect layer and as a charged body in SiO 2 , which has a large effect on the electronic state of the Si surface, and ultimately reduces the stability of the FET. It causes problems with sexuality.
Based on the above reasons, careful handling is required during the manufacturing process, and the above MOS-FET,
Furthermore, in general, a high purity quartz tube is used as a reaction vessel due to concerns such as undesired impurity contamination and heat resistance during vapor phase growth such as oxide layer formation and impurity diffusion in the manufacture of MOS-ICs. As shown in FIG. 2, there is a gas introduction section for forming a reaction atmosphere at one end of the quartz tube 6 (excluding a part of the gas introduction tube 7, the gas source, gas amount adjustment device, etc. are not described). A semiconductor substrate support jig 18 having a semiconductor substrate 8 (not shown) with the other end open and supporting a semiconductor substrate 8 from the lever is inserted. This loading is carried out using a semiconductor substrate support jig moving rod 9 (hereinafter abbreviated as moving rod) as shown in FIG. The moving rod has a "key portion" 9a formed at its tip so that it can also be used to take out the semiconductor substrate support jig. The semiconductor substrate is heated by a high-frequency coil surrounded by a quartz tube, heated by a soaking tube, and subjected to a gas phase reaction in a predetermined atmosphere. When the reaction is completed and the temperature is lowered, the moving rod is inserted and operated (taken out) as shown in FIG. 3, and outside air (air) flows into the container by convection. The above causes Qss to warp on the semiconductor substrate.
(Surface State) increases. The above-mentioned warping has the disadvantage that, for example, the precision of the pattern is reduced due to poor press-fitting of the mask during photolithography, and fine patterning is impaired. Furthermore, an increase in Qss has a serious drawback in that it deteriorates the layer quality of an example of a SiO 2 layer formed on a semiconductor substrate. (The above
Qss represents the effective total charge present in the interfacial system,
It is expressed by the following formula: Qss=Vss×Cox. In the above equation, Cox is the charge capacity of the oxide film, and Vss≡Vth−V 1 th, where Vth is the “threshold voltage” and V 1 th is the “intrinsic threshold voltage.” do. ) The present invention provides an improved semiconductor substrate vapor phase reactor for eliminating the drawbacks of the conventional vapor phase reactors described above. A vapor phase reaction apparatus for semiconductor substrates according to the present invention includes a heat-resistant vapor phase reaction vessel having a gas outlet at one end and closed at the other end with a lid, a heating means surrounding the reaction vessel, and a heating means for surrounding the reaction vessel. In a semiconductor substrate phase inversion device comprising a reaction gas introduction part for introducing a reaction gas for performing a gas phase reaction on a semiconductor substrate placed on a semiconductor substrate support jig in a container, the lid has a flat part; It has a side part extending from the flat part at the periphery of the flat part, and at least a part of the side part loosely fits into the open end of the reaction vessel, closes it, and connects to the flat part. It is characterized by having an opening through which the provided semiconductor substrate support jig passes, and a cutout extending from the opening to the side surface. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings regarding an embodiment of a vapor phase reaction apparatus for a semiconductor substrate. In FIG. 4, which is a side cross-sectional view, 6 is a quartz tube of the reaction vessel, and at one end there is a gas introduction part 7 for forming a reaction atmosphere (except for a part of the gas introduction tube, there is no gas source, A semiconductor substrate support jig 18 is installed in which the semiconductor substrate 8 is supported by a lever with the other end open. This charging is carried out using a moving rod 9 as shown in FIGS. 6 and 7. Note that the moving rod has a "key portion" formed at its tip so that it can also be used to take out the semiconductor substrate support jig.
The semiconductor substrate is heated by a high-frequency coil surrounded by a quartz tube, heated by a soaking tube, and subjected to a gas phase reaction in a predetermined atmosphere. When the reaction is completed, the lid 10 as shown in FIGS. 4 and 5
is attached to the open end of the quartz tube 6. The lid body is made of quartz, which is the same material as the quartz tube 6, and is shown in FIG.
Figure b is a side view viewed from the axial direction, Figure b is a side cross-sectional view,
As shown in the bottom view in FIG. It fits loosely into the side surface of the quartz tube 6 at the part and becomes detachable. Further, the opening 10c' is extended to the side surface portion 10b to form a cutout portion 10c. According to the present invention, since convection of outside air is prevented from flowing into the reaction vessel, the warpage of the semiconductor substrate and the Qss
This has the significant advantage of preventing the increase in That is, the warpage causes a decrease in pattern accuracy due to poor press contact of the mask during photolithography, as an example, and fine patterning is impaired. Also, the increase in Qss is MOS−
Damages the electrical characteristics of FETs and MOS-ICs. The present invention has reduced the variation in Vth value in an example of a MOS IC from the conventional ±0.36v to ±0.12v. Next, according to the shape of the lid according to the present invention, when it is fitted onto the end of the quartz tube of the gas phase reaction vessel as shown in FIG. 6, the moving rod 9 can be easily inserted. Also the 7th
As shown in the figure, since the angle (θ) for moving the rod up and down can be widely tolerated, the rod will not break even if the installation height of the reaction container is considerably different from the height of the operator of the moving rod. It has advantages such as easy operation.
第1図はMOS―FETの一部の断面図、第2図
は半導体基板の気相反応装置の一部の断面図、第
3図は第2図の装置の操作を説明するための断面
図、第4図は本発明の一実施例の気相反応装置を
説明するための側面断面図、第5図は第4図の一
部のふた体を示す図aは軸線方向から視た側面
図、図bは側面断面図、図cは下面図、第6図お
よび第7図はいずれも本発明を説明するための斜
視図である。なお図中同一符号は同一または相当
部分を夫々示すものとする。
6……石英管(反応容器)、8……半導体基
板、9……半導体基板支持治具移動用棒体、10
……ふた体、10a……平面部、10b……側面
部、10c……切抜部。
Figure 1 is a cross-sectional view of a part of a MOS-FET, Figure 2 is a cross-sectional view of a part of a semiconductor substrate vapor phase reaction device, and Figure 3 is a cross-sectional view for explaining the operation of the device shown in Figure 2. , FIG. 4 is a side cross-sectional view for explaining a gas phase reactor according to an embodiment of the present invention, and FIG. 5 is a side view showing a part of the lid in FIG. 4. FIG. , Figure b is a side sectional view, Figure c is a bottom view, and Figures 6 and 7 are perspective views for explaining the present invention. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 6... Quartz tube (reaction vessel), 8... Semiconductor substrate, 9... Rod for moving semiconductor substrate support jig, 10
... Lid body, 10a ... Plane part, 10b ... Side part, 10c ... Cutout part.
Claims (1)
塞される耐熱性の気相反応容器、前記反応容器を
取囲む加熱手段、前記反応容器内に半導体基板支
持治具に載置された半導体基板に気相反応を施す
ための反応ガスを導入する反応ガス導入部を具備
した半導体基板反応装置において、ふた体が、平
面部と、この平面部の周縁にてこの平面部から延
在された側面部を有し、かつこの側面部は少くと
も一部が反応容器の開端と遊嵌しこれを閉塞する
ともに、平面部に設けられた半導体基板支持治具
を通過させる開孔とこれを側面部に延長した切抜
部を有することを特徴とする半導体基板の気相反
応装置。1. A heat-resistant gas phase reaction vessel having a gas outlet at one end and closed with a lid at the other end, a heating means surrounding the reaction vessel, and a semiconductor substrate support jig placed within the reaction vessel. In a semiconductor substrate reactor equipped with a reaction gas introduction part for introducing a reaction gas for performing a gas phase reaction on a semiconductor substrate, the lid has a flat part and a lid extending from the flat part at the periphery of the flat part. At least a part of the side surface part loosely fits into and closes the open end of the reaction vessel, and has an opening provided in the flat part through which a semiconductor substrate support jig is passed. 1. A gas phase reaction device for a semiconductor substrate, characterized in that the semiconductor substrate has a cutout portion extending to a side surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5647377A JPS53142177A (en) | 1977-05-18 | 1977-05-18 | Vapor-phase reaction device for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5647377A JPS53142177A (en) | 1977-05-18 | 1977-05-18 | Vapor-phase reaction device for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53142177A JPS53142177A (en) | 1978-12-11 |
| JPS6225254B2 true JPS6225254B2 (en) | 1987-06-02 |
Family
ID=13028065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5647377A Granted JPS53142177A (en) | 1977-05-18 | 1977-05-18 | Vapor-phase reaction device for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53142177A (en) |
-
1977
- 1977-05-18 JP JP5647377A patent/JPS53142177A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53142177A (en) | 1978-12-11 |
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