JPS622737A - Decoder with addressing - Google Patents

Abstract

PURPOSE:To decrease the number of bits of a transmission signal by preparing the address bit maps for each decoder when addressing operation is carried out to the decoder having continuous address numbers and then transmitting the address bit map data (binary data). CONSTITUTION:When an addressing operation is performed to a decoder having continuous address numbers, an address bit map data AM is prepared to each decoder for transmission of the address bit map data (binary data) AD. This data AD can be also used as the addressing bit data. Thus it is not needed to send the addressing data in addition to the address data even in case the addressing operation is required independently. In such a way the number of bits of a transmission signal is decreased.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem F. Effect G. Example G1. Outline explanation of the information service system G2. Basics of the information service system System diagram showing a schematic configuration (Figure 1) Format of the transmission signal inserted into the G3 broadcast signal (Figure 2) Format of the service data section SD before G4 shuffling (Figure 3) G5 service data section SD Formant showing the relationship between the following service data SDA (Fig. 4) Explanation of the G6 baud rate section BR (Fig. 5) Explanation of the G7 control data section CD (Fig. 6) Explanation of the G8 sync code SC (Fig. 7) Figure) Explanation of G9 control data CDA (Figure 8) Explanation of GIG addressing (Figure 9) Format of G11 addressing data AD (Figure 9) 012 Reason for using 2 types of key codes G, 3 Multiple addressing Reason for setting the mode System diagram of GI4 receiver 30 (Figure 11) GIS decoder 500 circuit explanation (Figure 12) G16 service data SD
Decoding process of A G, 7 Decoding process in addressing mode GI8 Sync code detection unit 60 and judgment circuit unit 5
Explanation of 9 (Fig. 13) H Effects of the Invention A Industrial Application Field This invention can be applied to a new information service system in which information data can be kept confidential and information services can be provided for a fee. Relating to a preferred addressed decoder.

B. Summary of the Invention The present invention relates to an information service system in which information data is concealed and information services are charged.

This information service system receives the service data and key code sent from the database station using a decoder installed on the subscriber side, and the key code sent after decoding these data matches the key code on the receiving side. This system allows users to receive specific information services sent out from database stations only when they do so.

This invention relates to a decoder with addressing used in such an information service system. When addressing decoders with consecutive address numbers, an address bitmap corresponding to each decoder is prepared, and this address bit map is prepared for each decoder. It is designed to send out bitmap data (binary data) for
Thereby, this addressing focus map data can also be used as bit data for addressing.

C. PRIOR TECHNOLOGY As an information service system that allows specific information to be provided only to specific subscribers, systems that utilize a dedicated line have been known for some time.

Specifically, specific information transmitted from the database station using a dedicated line is received by a decoder installed on the subscriber side, and the information provided by the station side can be received. There is.

D. Problems to be Solved by the Invention However, the above-mentioned information service system has a limit because it becomes difficult to secure a dedicated line when the number of subscribers increases significantly.

In addition, if the information provided by the station requires a large amount of money to collect the information and provide information transmission equipment, such as stock information or commodity trading information in multiple markets, non-subscribers may It is necessary to devise a system in which the information cannot be easily decoded. In conventional information service systems, information can be easily obtained by simply installing a decoder on the subscriber side, so even non-subscribers can easily obtain the information.

In such a case, it is necessary to take advanced measures to prevent wiretapping, but conventionally such concealment measures have not been adopted.

Furthermore, conventionally, once a decoder is purchased, information can always be provided as long as the user owns the decoder. However, as mentioned above, when the cost of collecting information and the cost of equipment for station operation are enormous, it is preferable to provide the information for a fee.

Therefore, an information service system that targets a large number of subscribers, ensures confidentiality of information, and charges a fee has not yet been developed.

This invention takes these points into consideration, and proposes an addressing means on the decoder side that is necessary for a paid service system, in particular, the problems encountered when configuring an information service system that can realize information confidentiality and paid information services. It is.

E. Means for Solving the Problems In order to solve the above-mentioned problems, the present invention employs the following means.

That is, in this invention, the service data and key code sent from the database station are received by a decoder provided on the subscriber side, and the key code sent after decoding these data matches the key code on the receiving side. When addressing a decoder, the address map data assigned to each decoder is used for each decoder. It can also be used as an addressing code for

F Function In this configuration, when addressing decoders with consecutive address numbers, an address bitmap corresponding to each decoder is prepared and this address bitmap data (binary data) is sent. , this address bitmap data can also be used as atranging data.

Therefore, even when addressing must be performed individually, it is no longer necessary to send addressing data in addition to the address data, resulting in effects such as being able to reduce the number of bits of the transmission signal.

G. Embodiment FIG. 1 is a schematic configuration diagram showing an example of an information service system that is the premise of this invention.
An outline of the information service system according to the present invention will be explained.

G. Explanation of the Information Service System Shield This information service system, as described above, receives the service data and key code sent from the database station with a decoder installed on the subscriber side, and decodes these data. A system in which a specific information service sent from a database station can be received only when the key code sent by the database station matches the key code on the receiving side.

The first feature is that the transmitted data is shuffled to prevent eavesdropping.

This is to make it difficult for non-subscribers to obtain information and to provide specific information only to specified subscribers, as described above.

Second, information services are charged.

In other words, the system is such that only those who have paid the fee can receive information services.

To this end, in this system, a reception contract period, for example, a monthly reception contract period, is determined, and information can be continuously provided by updating the contract period.

Payment of fees for each reception contract period and non-payment are checked on the station side, and if the fees are not paid, the information service is automatically stopped, so the addressing on the decoder side, which will be described later, is the same as data transmission. carried out by means.

Therefore, after addressing, a key code is transmitted at the same time as the data transmission described above, and only when the transmitted key code matches the key code stored in the receiver's decoder (the key code stored by addressing), information is sent. You can receive the offer.

System diagram showing the basic schematic configuration of the G2 information service system Now, FIG. 1 is a configuration diagram showing an example of a new information service system 10 that is the premise of the present invention.

10A is a database station, IOB is a ground relay station, 10C
is a receiving station (subscribing station), and the transmission signal formed by the database station 10A is inserted into a predetermined horizontal line or several horizontal lines in the vertical blanking period of the broadcast signal, and the broadcast signal into which the transmission signal is inserted is (The format is shown in FIG. 2) is transmitted to the broadcasting satellite 22, and from the broadcasting satellite 22 this broadcasting signal is transmitted to the terrestrial relay station 10B.

The terrestrial relay station 10B has a BS antenna 24, and the SHF band broadcast signal received by this antenna is supplied to a transmitter 26 via a BS converter 25, and the broadcast signal is converted into a UHF or VHF band suitable for retransmission. While being converted into a broadcast signal, this is fed to the antenna 27 and transmitted to a plurality of receiving stations 1.
Sent towards 0C.

The broadcast signal received by the antenna 29 of the receiving station 10C is decoded by the transmission signal inserted into the broadcast signal in the receiver 30, and the service data obtained as a result of the decoding is supplied to the personal computer 31, and the necessary information is Once selected, it is provided to the monitor 32 to monitor its data.

Assuming that a maximum of 8 horizontal lines (8 channels) are used as a transmission signal to be inserted into a broadcast signal, it is possible to install multiple databases IIA-11H in the database station 10A, and therefore 8 databases IIA-11H according to the number of channels mentioned above. can.

Each of the databases 11A to IIH includes large host computers 12A to 12H and a pilling computer 13A corresponding to each database.
~13H will be installed. Hosujo Koneta collects stock information, product transaction information, etc. for each region and provides service information data (hereinafter referred to as service data) to customers.
is formed.

The pilling computer manages the reception contract status of each subscriber subscribed to each database, and creates pilling data, ie, addressing data, corresponding to the reception contract and its cancellation for each reception contract period.

Service data and pilling data are supplied to corresponding processors (front end processors, FEPs) 14A to 14H using telephone lines or dedicated lines. One processor can process one channel of data, where one data channel corresponds to one horizontal line inserted into the video signal.

Each of the processors 14A to 14H has eight data input ports, and can multiplex up to eight types of service levels for one channel. Therefore,
As shown in FIG. 1, the service data transmitted from the first database IIA is transmitted to all processors 14A-1.
It is designed so that it can be input to the 4H port. 2nd ~
The same applies to the service data from the eighth database IIB-11). Therefore, the eight processors 14A
Up to 64 types of service data can be handled in ~14H.

Each of the processors 14A to 14H is connected to a host computer 15 that generates control data, etc., which will be described later, and a shuffled transmission signal is formed based on these data.

The transmission signal is superimposed on the video signal supplied to the terminal 18 in the data insertion circuit 17 . Which horizontal line in the vertical blanking period the transmission signal is inserted into is determined by a control signal (not shown) supplied thereto.

The broadcast signal into which the transmission signal has been inserted is sent to the transmitter 2o and 7S.
After being converted into an HF band signal, it is transmitted to a broadcasting satellite 22 by a BS antenna 21.

Format of the transmission signal inserted into the G3 broadcast signal Now, Figure 2 shows an example of the format of the transmission signal (one horizontal line) that is superimposed on the broadcast signal. Part SD (21 bytes in this example) ■, Check pit part CB for this service data part SD (10 bytes) ■, Control data part CD inserted at the front of the service data part SD (1 byte) ■, Control data Bit sync (2 bytes) inserted at the front of the CD
It is composed of a synchronous data section (1) consisting of BIS and byte sync BYS (1 byte), and a channel address section CA (1 byte) inserted between the synchronous data section and control data section CD.

The synchronous data section is clock data inserted to decode the transmission signal.

The channel address section CA is data indicating the type of channel used.

The control data portion CD is data indicating shuffling block data, shuffling map data, etc. for the shuffled service data portion SD, etc., and this control data portion CD is also transmitted in a shuffled state.

The service data section SD is data provided for customer services such as securities information.

G. Format of service data section SD before shuffling FIG. 3 shows the format of service data section SD before shuffling.

In this example, the service data section SD has 62 fields (
62 lines) as one data block, and one data block further consists of eight service blocks (SB,
~5Ba).

The data inserted into the water supply rate line of the nibbuter block is 31 bytes, and one service block consists of 31 bits.

The data inserted into the first field before shuffling is the header data portion HD, and the second field and subsequent fields are service data SDA.

The header data portion HD is used as decoding information (service data multiplexing information, etc.) for the service data SDA inserted below the second field.

G5 Format showing the relationship between the service data section SD and the following service data SDA FIG. 4 is a format showing the relationship between the service data section SD and the following service data SDA.

That is, in the first horizontal line corresponding to the first field, a header data section HD having a format as shown in the figure is located for each service block. The header data section HD is as follows: (1) Service level section sL (3 bits) This indicates data indicating which channel is used to insert service data.

(2) Baud rate section BR (2 bits) This is because the configuration of the service block during transmission differs depending on the baud rate. The details will be described later.

■, Sync/Async (SYNC/ASYNC) section 5A
S (1 bit) Data indicating whether data is transmitted in synchronous mode or asynchronous mode.

■Key code section KC (4 bits) A key code inserted for each service of the month so that only paid subscribers can receive the information service. It is compared with the key code sent to the decoder, and if they match, the data service is executed.

(2) Line data end portion LDE (6 bits) Since the length of the blocks constituting one service block is different for each service block, this data indicates the number of lines constituting the block.

In the case shown in FIG. 4, the service block ends at the 58th line, so in this case, data indicating that the 58th line is the last line is inserted as the line data end part LDE. .

■Bit data end part BDE (5 bits) This data indicates the number of bits in the final line of the service block. In the example shown in Figure 4, the 10th bit is the final bit, so this final bit is It is expressed by the data end part BDE.

formatted like this.

Even after shuffling, the header data portion HD having such a format is applied to the first horizontal line of each service block.

G6 Description of baud rate section BR The structure of the service block during transmission differs depending on the baud rate section BR.

For example, when the transmission capacity is up to 9600 baud,
When the transmission rate is set to 9600 po, the first to eighth service blocks SB, ~SB
Data composed of days is only one channel data, and when composed at 4800 baud, two channels of data can be transmitted as shown in Figure B.

Examples of other baud rates are shown in C and D of the same figure. however,
In addition, 2400 baud and 1200 baud can be selected, so it is easy to understand that combinations other than those shown in the example may also be used.

The header data section HD, service data SDA and check bit section CB described above are shuffled within each line and also between 62 lines.

However, even after shirtling, the service data section SD inserted into the first horizontal line of one block data
Processing in which the above-described header data section HD is located is executed by the processors 14A to 14H.

G7 Description of Control Data Section CD FIGS. 6 to 8 are used to explain the contents of the control data section CD.

The control data section CD is also shuffled except for some data, and an example of the structure of the control data section CD corresponding to one block after being deshuffled is shown in FIG.

The control data section CD has a variable length data structure, which is as follows: 1) sync code SC (1 byte) 2) control data CDA (48 bytes fixed length) 2) dummy code DC (4 to 11 bytes variable length) long code).

The sync code SC is used as data information for deshuffling the shuffled control data portion CD and as data information indicating a division of the control data portion CD. When using 64 types of sync codes as the sync code SC, the control data section CD
You can select from 64 different shuffling patterns.

Description of G8 Sync Code SC The sync code SC has not been subjected to shuffling processing. A sync code SC is considered to be a sync code SC only when the same code is inserted three times in succession.

That is, as shown in FIG. 7, this sync code SC is inserted from the first line to the third line.

The 48 bytes of data following the sync code SC becomes control data CDA.

The control data CDA includes shuffling block information of the service data section SD transmitted to the decoder 50 (see FIG. 12) and its shuffling map information.

G9 Description of Control Data CDA FIG. 8 shows an example of the format of control data CDA (before shuffling).

The control data CDA is composed of 4 bytes as a basic unit, and the first 2 bytes are shuffling block data S.
In B, the last two bytes are shuffling map data SM.

First, shuffling block data SB is formed with a total of 6 bits: 2 bits in the first byte and 4 bits in the second byte. . Check code C inserted into each byte
C is for data checking of shuffling block data SB inserted into each byte.

The shuffling map data SM is formed by a total of 6 bits consisting of 2 bits in the third byte and 4 bits in the fourth byte. The check code CC inserted into each byte is for checking the shuffling map data SM inserted into each byte.

The same code as this control data CDA is repeated 5 times (
A total of 20 bytes) are inserted, so the format before shuffling is as shown in FIG.

The reason why the same data is used five times in this way is to avoid malfunctions caused by noise mixed in during transmission. It is used as control data CDA.

The control data section CD has a fixed length of 48 bytes, and the data following the above-mentioned control data CDA is used as optional data. Therefore, data slots after 20 bytes are not used as control data.

The dummy code DC inserted at the rear of the control data CDA has a variable length, so that the code length of the entire control data section CD has a variable length configuration. In this example, the control data section CD is varied over 55 to 62 fields, and therefore the dummy code DC is 4 to 62 fields.
This is any code length between 11 fields. As a result, in the control data section CD, 55 to 62 fields constitute one block.

The dummy code DC uses a code pattern that is not present in the sync code SC. This is the control data part C
This is to accurately separate the sync code SC from D.

If the control data section CD is configured to have a variable length, it becomes difficult to detect the control data section CD inserted into one block, which complicates the data deshuffling process by non-subscribers and reduces the confidentiality of information. will be strengthened.

Furthermore, the control data section CD includes a sync code SC that has not been shuffled, but even if the sync code SC has not been shuffled, the code length of the control data section CD itself is variable. The control data section CD cannot be easily decoded.

However, the decoder installed by the subscriber has a deshuffling pattern ma knob that detects the sync code SC and deshuffles the control data section CD, so for that decoder, the control data section CD is Deshuffling processing can be performed accurately.

In this case, since the data (length: 48 bytes) following the sync code SC is constant, it is relatively easy to detect the sync code SC on the decoder side.

As described above, the control data section CD is shuffled according to the type of sync code SC, and by decoding the shuffling map data SM included in the shuffled control data CDA,
The service data portion SD will be deshuffled.

The service data section SD and control data section CD shuffled in this way are inserted into one horizontal line in units of 31 bytes, thereby forming the format of the transmission signal shown in FIG. 2. In this case, the synchronization data (see FIG. 2) inserted into each horizontal line is not shuffled.

Description of GIG Addressing Before transmitting the transmission signal shown in FIG. 2, addressing is performed on the decoder 50 provided in the receiver 30.

Addressing is also performed using broadcast signals as well as transmission signals. In this case, among the transmission signals shown in FIG. 2, one in which addressing data ADA is inserted instead of service data SDA is used as the transmission signal.

First, an overview of addressing will be explained.

The plurality of decoders provided in the plurality of receiving stations 10C include
A non-volatile memory is provided to store the key code.
The key code transmitted during addressing is stored in these memories. Consecutive addresses are attached to the decoder, and when an address that specifies the decoder (address map may be used) is transmitted, it enters the key code waiting state, and the binary code of the address map becomes '1''. The writing state of the key code is automatically controlled depending on whether the key code is '0' or '0'.

For example, if the binary code is ``1'' to enable writing, when the binary code of the address map is 1'', the corresponding decoder will
The key code will be written. Therefore, in this case, when the binary code is "1", it means that the reception contract fee has been paid.

When the binary code is 0'', the reception contract fee has not been paid, so in that case the key code is not stored in the corresponding decoder.

Addressing is performed for each reception contract period, and the addressing period is performed using a predetermined period before the reception contract period (which may extend into the next month's reception contract period).

As shown in Figure 2, the current month's key code KC is inserted into the transmission signal, so the information service is only received when this key code KC matches the key code stored in the decoder. be able to.

Therefore, the format shown in FIG. 9 is adopted for the addressing data AD.

Format of Gl+Addressing Data AD Addressing data AD is also constructed of 62 fields as one block, and is subjected to shuffling processing to conceal information.

The format shown in FIG. 9 is for one horizontal line before shuffling.

Addressing data AD is configured as follows.

■Key code KC (1 byte) Two types of key codes are sent. The key code has a 4-bit configuration, one of which is the current month's key code, and the remaining one is the next month's key code.

When the decoder receives the service data SDA, if either of the two key codes is stored in the memory, the decoder enters the service state.

■, address data AD1, AD2 (3 bytes each)
Address data AD is address data for specifying a decoder, and although it differs depending on the mode code at the time of addressing, which will be described later.

With data from AD2 to AD2, decoder addresses can be specified in units of 100 units.

However, this address data cannot specify a specific decoder address.

(2) Address map data AM (13 bytes) Addresses are specified for 104 decoders based on the address of address data ADI (AD2).

The first l bits of the address map are address data A.
The address of each decoder is sequentially specified so that the address is for the same decoder as D+ (A D2 ), and the next 1 bit is the address for the next decoder.

Address data A D 1, A D 2 and address map data AM have different addressing specifications depending on the mode code MD described below. - ■Mode code MD (2 bits) This is a code for specifying the mode during addressing.

Since it has a 2-bit configuration, the following four types of addressing modes can be selected.

(a) Mode O This is a batch addressing mode in which data service is not provided to all decoders having addresses specified by address data AD, AD2.

In this case, all bits of the address map data AM are set to aO'', and the transmitted key code KC is not stored in the memory of the decoder.

(b), Mode 1 A mode in which data service is provided to the decoder specified by the address of address data AD and the decoder specified by the address of address data AD2 (therefore, only two decoders are specified). be.

(C1, Mode 2 For each of the 104 decoders whose addresses are based on address data AD 1, AD 2, at-I+, '0'' of the address map AM following this address data AD, AD2. Addressing is performed by

In this case, address data A DI , A D
2 are the same address data.

If the address data AD+ specifies a decoder in the 100s, the first bit of the address map AM is 10.
Specifies the 0th decoder and the following bits are 101
This will specify the second decoder.

When that bit is "1", the above-mentioned key codes (two types) are stored in the memory of the corresponding decoder.

On the other hand, when the bit is "O", no key code is stored.

(d), Mode 3, which is the opposite of mode O, addresses all decoders specified by address data AD, . . . AD2 at once.

Therefore, key codes will be stored in those decoders. In this case, address map data AM is set to all "1"s.

(2) Service level code 5L (6 bits) This is a code indicating which host computer's data was inserted into which channel for transmission. The upper three bits are allocated to the data channel, and the lower three bits are allocated to the service level.

In the above example, eight host computers and eight horizontal lines (eight channels) are used for transmission, so a total of 64 types of service levels can be specified.

G12 Reason for using two types of key codes In the above addressing format, first two types of key codes KC and KC are used.
The reason for sending out the two at the same time is as follows.

Addressing is performed in units of reception contract periods before the contract period expires. For example, if the contract period is determined on a monthly basis, next month's addressing will be executed in the current month. The key code (in the transmission signal) sent during the contract period uses a key code with a different pattern from the previous key code, so if only the next month's key code (one type) is sent during addressing,
The following inconvenient situations occur.

For example, as shown in Figure 10, the current month is January,
It is assumed that KC, is used as the key code KC for January, and KC2 is used as the key code KC for February.

In this case, addressing using the key code KC2 is executed during period T in the latter half of January. If a particular decoder has been paid the reception contract fee for both January and February, that particular decoder will store the key code KC2 in a predetermined memory during addressing in mode 2.

As a result of this memory operation, the key code KC2 for January is stored in this memory instead of the key code KC.

Therefore, since the key code will be changed to KC2 from the second half of January, there will be inconveniences such as not being able to receive data service even though the reception contract fee has been paid during the second half of the period after addressing. occurs.

On the other hand, as mentioned above, when addressing the current month and the next month's key codes KC1 and KC2 at the same time and executing atranging at the same time, the key codes KC1 and KO2 are both stored in memory. , even after addressing, the data service for that month can be received, and the above-mentioned inconvenience is solved.

CI3 Reasons for setting multiple addressing modes The reason why multiple addressing modes can be selected is based on the following reasons.

For example, if the receiving station 10A, which has all decoders for addresses in the 0 to 1000 range, has not yet paid the reception contract fee, batch addressing using mode 0 is preferable to performing addressing individually using mode 2. This can significantly reduce the time required for addressing.

For the same reason, when the reception contract fee for a certain receiving station 10A is paid, if you execute addressing in mode 3, addressing will be done in bulk in this case as well, and the addressing time can be greatly reduced. It is.

However, when the reception contract fee is paid differently depending on the address, by selecting mode 2, addressing can be performed according to the contract status of each receiving station 10A.

In addition, when addressing a specific receiving station among the plurality of receiving stations 10A, it is necessary to perform addressing in mode 2, but if mode 1 can be selected as described above, it is possible to Since only those receiving stations are addressed immediately, the addressing time can be reduced compared to when mode 2 is selected.

For this reason, by selecting the addressing mode according to the reception contract status, even if there are a large number of subscribers, the addressing time for all subscribers can be shortened.

FIG. 11 shows an example of a receiver 30 installed in the receiving station 10A for receiving a transmission signal having the above format and receiving a specific data service.

The broadcast signal received by the system diagram antenna 29 of the G14 receiver 30 is supplied to a tuner 40 with an all-channel configuration, where it is converted into a television signal in a predetermined frequency band, and this is supplied to a ghost canceller 41 for ghost cancellation. Processing is performed to avoid data extraction malfunctions.

The output is supplied to a data separation circuit 42, where the transmission signal inserted into the broadcast signal is extracted and separated. The extracted transmission signal is supplied to a decoder 50 and service data S
Decoding processing such as DA is executed. The service data SDA is converted into a code format that conforms to the standards of the personal computer 31 and is then supplied to the personal computer 31 via the interface 43 .

44 is a control system, which is a controller 45,
It is comprised of a keyboard 46 for giving commands. 4
7゛ is a power supply device.

Circuit Description of CI5 Decoder 50 FIG. 12 is a system diagram showing an example of the above-mentioned decoder 50. The transmission signal separated by the data separation section 42 is subjected to byte sync BYS extraction in the byte sync section 51.

To detect the byte sync BYS, a gate signal is generated in advance by the gate pulse generator 52 using the horizontal and vertical synchronizing signals HD, VD and the clock signal CK, and the vicinity of the byte sync BYS is gated with this gate signal, and then detected.

When the byte sync BYS is detected, the detection signal is input to the gate pulse generator 52, which is used as a gate to extract the channel address CA, control data section CD, service data section CD, addressing data AD, etc. based on the byte sync BYS. A signal is created.

The channel address data CA extracted by the channel address gate section 54 is sent to the error correction (hamming) section 5.
5, and the error is corrected.

The error-corrected 4-bit channel address data CA is compared with the 4-bit channel address setting data sent from the controller 45 in the channel address comparing section 56, and if they match, the gate pulse generating section 52
sends a match signal to

The gate pulse generator 52 uses this coincidence signal as a reference to gate the insertion timing of channel address data on the same line in the next field. Similarly, gate pulses are output to the data gate 57 and control data gate 58.

The control data section CD extracted by the control data gate 58 is sent to the sync code detection section 60 to detect the sync code SC included in the control data section CD, and 64 types of sync codes SC are extracted. .

Here, when the same sync code SC is detected over three fields, it is sent as the sync code SC to the determination circuit section 59 as a sync detection signal. When the determination circuit section 59 receives this detection signal, it sends a holding signal to the sync pattern holding section 70 for holding the sync code SC.

Further, a gate signal for detecting the sync code of the next control data section CD is sent to the sync code detection section 59.

This allows the sync code SC to be easily detected. The details will be described later.

When the sync code SC is detected, the judgment circuit section 59 tells the timing generating section 72 to perform deshuffling according to the type of the sync code SC at the same time as writing the control data CDA itself to the RAM 73 following the sync code SC. Sends a sync detection signal that starts the process.

The deshuffling pattern generating section 75 receives a pattern code (6 bits) from the sync pattern holding section 70 and generates a deshuffling pattern that becomes a write address of the RAM 73. The start signal is output from the timing generator 72.

When the control data CDA is read from the RAM 73, it is deshuffled.

For this reading, the read counter 74 operates in response to a counter start signal from the timing generating section 72, and at the same time, the address switching section 76 is switched to the read side and a read signal is supplied to the RAM 73.

The read control data CDA is error-corrected by an error correction (hamming) section 80, and further, by a holding signal generated by a timing generation section 72, a data block information extraction section 81 converts data block information SB into deshuffling information. The extraction section 82 extracts the deshuffling map information SM and uses it as a key signal for reproducing the data part.

Service data SDA (
Alternatively, addressing data ADA) is stored in a data buffer 85 and sent to a deshuffling circuit 86, which is controlled by a buffer control section 87.

The buffer control section 87 receives a reference signal indicating the position (field) of the sync code in the control data CDA from the determination circuit section 60 and the data block information section 81.
It receives the data block shift information from , stores the service data 5DA (or addressing data ADA) block by block in the data buffer 85, and then performs control to send it out.

The deshuffling circuit 86 is the deshuffling information unit 8
2, the deshuffling pattern information SM is input, and the service data is deshuffled. After that, service data SDA (or addressing data A
DA) is error corrected by an error correction circuit 91.

Note that when a data transmission failure occurs, a data reset signal is sent from the gate pulse R generation unit 52 to the buffer control unit 87, and the data in one block stored until the data transmission failure occurs is sent. Data is cleared.

Similarly, this data reset signal is also supplied to the control data processing system to clear the data.

Specifically, the above-mentioned data end information is supplied to each of the deshuffling pattern generation section 75, the data block information extraction section 81, and the deshuffling information extraction section 82.

On the other hand, RAMI 10 for data storage has a larger transmission capacity (9900 baud) than the normal transmission rate (9600 baud).
The capacity is selected so as to be able to store data (port), so that even if a transmission failure as described above occurs, data can be sent to the subsequent interface 43 without interruption. This processing mode is a so-called catch-up mode.

Decoding process of CI6 service data SDA When the addressing mode detection unit 100 detects the service mode, the error-corrected service data part SD (
1 data block) 1st line belly button part H
Service level code detection unit 10 to read the information of D.
11 baud rate detection section 102, sync/async detection section 103, data end detection section 104, and key code detection section 105 each operate to detect each piece of information.

The detected service level code SL is compared with the service level code sent from the controller 45 in the service level comparison section 107, and if they match, a match signal is sent to the buffer control section 108 and the key code comparison section 109.

The detected key code is compared with a predetermined key code stored at the time of addressing in key code comparison section 109, and if they match, a match signal is sent to buffer control section 108.

The buffer control unit 108 performs control to buffer necessary data in the RAM 110 based on the service level match signal, key code match signal, baud rate information, and data end information, and output it to the interface 43 at a constant rate.

A boat rate signal and a sync/async signal are also sent to the interface 43.

G, 7 Decoding process in addressing mode In the addressing mode, each line of the data block serves as addressing information.

Therefore, for each line, mode signal MC, service level code SL, key code KC, address data AD
7. AD2, detect address data map AM.

Therefore, in addition to the mode code detection section 112, a service level code detection section 121, a key code KC detection section 122, an address data AD detection section 123, an address data AD2 detection section 124, and an address data map AM detection section. portions 125 are provided, respectively.

Mode code M detected by mode code detection unit 112
C is sent to the address data ID comparison section 113. The address data ID comparison unit 113 compares the sent address data with the ID (address data) unique to each decoder stored in the nonvolatile memory 114. Before this comparison, the mode code is
, , A D 2 is a code for processing the address data map AM according to the format.

When a match with the output of the decoder ID holding unit 115 is detected, an ID matching signal is sent to the memory control unit 116, and the memory control unit 116 selects the key code (two types) at this time.
is stored in the nonvolatile memory 114. At this time, the address of the non-volatile memory 114 is 6 of the service level code.
This is bit information (channel address 3 bits, service level 3 bits).

The address selector 120 selects the service level code SL sent in the addressing mode,
In the service mode, the channel address data CA sent from the controller 45 and the service level setting value are selected.

In the service mode, the key code stored in the set channel address and service level is read out from the non-volatile memory 114 and sent to the key code comparison unit 109.
sent to.

ate sink detection section 60 and judgment circuit section 59 explanation 13th
The figure is a system diagram showing the relationship between the sync code detection section 60 and the judgment circuit section 59, and the sync code detection section 60 is composed of a sync comparison section 61 and a sync pattern comparison section 62.
Each data in the control data section CD gated by the control data gate section 58 is converted into 8-bit parallel data by the shift register 65, and then supplied to the sync comparison section 61, and the pattern of the sync code SC is 64.
A comparison is made to see which pattern among the types of sync patterns matches.

If the pattern matches any of the 64 types of patterns, the match signal from the sync comparison section 61 is supplied to the sync pattern comparison section 62. The sync code SC itself is also supplied to the sync pattern comparison unit 62, and a comparison is made to see if the same sync pattern and matching signal have been input three times in a row.

When the same sync pattern is supplied over three fields, the sync pattern comparison section 62 outputs a sync detection signal.

The sync detection signal is supplied to the determination circuit section 59.

The determination circuit section 59 is composed of a counter timer, and a vertical synchronization pulse VD is supplied as its clock. The sync detection signal is used as a start signal for the counter timer, and the sync detection signal starts the counting operation.

When the counter timer counts 48 vertical synchronizing pulses VD, an "H" gate signal is output. As a result, the final field of the control data CDA of <48 bytes following the sync code SC is detected.

For this reason, the 48-byte fixed-length control data CDA in the control data section CD is II L 1'', and the variable-length dummy code DC and the following 3-byte sync code SC are II L 1''. , a gate signal that becomes "H" is generated by this judgment circuit 59.

The gate signal is supplied to the sync pattern comparison section 62 as a masking signal, and the pattern comparison operation is prohibited during the period when the gate signal is "L", and the pattern comparison operation is executed only during the period when the gate signal is "H".

Since the sync code SC and the coincidence signal are supplied to the sync pattern comparison section 62 at any timing during the period when the gate signal is "H", even if the dummy code DC has a variable length, this dummy code DC The sync code SC following can be detected.

When the sync code detection section 60 and the judgment circuit section 59 are configured in this way, the sync code SC inserted into the control data section CD can be reliably detected even if the control data section CD has a variable length configuration. be able to.

Although the control data CDA may include the same pattern as the sync code SC, the dummy code DC input during the pattern comparison operation does not include the same pattern as the sync code SC. Together with this configuration, the detection accuracy of the sync code SC can be improved.

Note that the holding signal supplied to the sync pattern holding section 70, the sync Ml signal supplied to the timing generating section 72, and the reference signal supplied to the buffer control section 87 are all output at the same timing as the sync detection signal. be done.

As described in detail about the invention H, in the addressing decoder used in the above-mentioned new information service system, when addressing is performed for decoders with consecutive address numbers, the invention An address bitmap is prepared and this address bitmap data (binary data) is sent out, so that this address bitmap data can also be used as addressing bit data.

Therefore, even when addressing must be performed individually, it is no longer necessary to send addressing data in addition to the address data, resulting in effects such as being able to reduce the number of bits of the transmission signal.

Therefore, as described above, the present invention is suitable for application to a paid information service system that provides information only to specific Kadaikichi.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a schematic configuration of an information service system according to the present invention, FIG. 2 is a diagram showing a format of a transmission signal, FIG. 3 is a diagram showing a format of a service data section, and FIG. 4 is a diagram showing a service data section. FIG. 5 is a diagram showing the relationship between the baud rate and the service block, FIG. 6 is a diagram showing an example of the format of the control data section, and FIG. 7 is a diagram showing the relationship between the baud rate and the service block.
FIG. 8 shows the relationship between c and control data CDA.
Figure 9 shows an example of the format of control data CDA, Figure 9 shows an example of the format of addressing data, Figure 10 shows an explanatory diagram for the sync code SC, and Figure 11 shows an example of the receiver. Systematic diagram of main parts,
FIG. 12 is a system diagram showing an example of a decoder, and FIG. 13 is a system diagram showing a specific example of a sync code detection section and a discrimination circuit section. 10 is an information service system, IOA is a database station, IOB is a ground relay station, 10C is a receiving station, 12A to 12
115 is a host computer, 13A to 13H are pilling computers, 50 is a decoder, 59 is a judgment circuit section, 60 is a sync code detection section, and 87 is a bumper control section.

Claims (1)

[Claims] The service data and key code sent from the database station are received by a decoder provided on the subscriber side, and the key code sent after decoding the data becomes the key code on the receiving side. In an information service system in which a specific information service sent from the database station can be received only when a match is made, multiple decoders are set so that their address numbers are consecutive, and each decoder is When performing addressing, the minimum digit of the address number set for each decoder is selected as a binary code, and a 1-bit address code is assigned to each subsequent decoder based on this address number. Decoder with addressing.