JPS622760B2 - - Google Patents
Info
- Publication number
- JPS622760B2 JPS622760B2 JP54113310A JP11331079A JPS622760B2 JP S622760 B2 JPS622760 B2 JP S622760B2 JP 54113310 A JP54113310 A JP 54113310A JP 11331079 A JP11331079 A JP 11331079A JP S622760 B2 JPS622760 B2 JP S622760B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- central processing
- scanning device
- processing unit
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
Description
【発明の詳細な説明】
本発明は電子交換機における通話路信号の処理
方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for processing communication path signals in an electronic exchange.
従来、この種の信号処理方式は中央処理装置が
一括して集中制御を行なつている。 Conventionally, this type of signal processing system has been centrally controlled by a central processing unit.
例えば第１図に示すように、MF信号の受信制
御は、主記憶装置MMに格納されている制御情報
でもつて中央処理装置CPUから発生する周期起
動パルスを計数し16mS等の周期の都度トランク
TRKに対してMF信号の読み取り指令を発するこ
とにより行なつている。信号受信分配装置SRD
は中央処理装置CPUからこの指令情報を受信す
ると、信号走査装置SCNまたはリレー駆動装置
RCに対する指令かを識別した結果、走査装置
SCNを起動し、指令情報を転送するとともに走
査装置SCNは指定されたポイントのデータを読
み取り信号受信分配装置SRDを経由して中央処
理装置CPUへ返送する。次にプログラムされて
いる制御情報は読み取りデータの正常性のチエツ
クおよび２進符号の変換を行なつて次に処理に引
きつぐ。 For example, as shown in Figure 1, the reception control of the MF signal is performed by counting the periodic activation pulses generated from the central processing unit CPU using control information stored in the main memory MM.
This is done by issuing a command to read the MF signal to TRK. Signal reception distribution device SRD
When receiving this command information from the central processing unit CPU, the signal scanning device SCN or relay driving device
As a result of identifying the command for RC, the scanning device
The scanning device SCN starts up the SCN and transfers the command information, and at the same time, the scanning device SCN reads the data of the specified point and sends it back to the central processing unit CPU via the signal receiving and distributing device SRD. Next, the programmed control information is checked for the normality of the read data and converted into binary code, and then handed over to the next processing.
従つて、MF信号における信号出力幅およびパ
ルス間隔を考慮すると、16mS程度の周期で全回
線を走査しなければならず、逆に他局に対する信
号送出機能さらに回線の起呼、切断等の状態監視
機能およびトランクTRKのリレー制御等を考慮
しなければならない。さらに各通話路制御の他
に、入出力機器であるタイプライターTYP、プ
リンターPTR、表示装置CRT等のオフライン制
御も加わるため、呼量増に比例してより高能率な
中央処理装置CPUを選定しなければならずシス
テム全体の価格に大きく影響を与えている。例え
ば既存の中央処理装置CPUを利用したシステム
を構成する場合、システム呼量が中央処理装置
CPU―Ａの処理能力より若干多くなつてしまう
（10％ぐらい）時、中央処理装置CPU―Ａより１
段高い処理能力を持つた中央処理装置CPU―Ｂ
を利用することになる。しかしながらもし中央処
理装置CPU―ＢがCPU―Ａの1.5倍の処理能力を
有するとすれば価格は４倍から５倍にもなつてし
まうのが現状である。具体的には現状に電子交換
機における通話路制御機能に関し、CPU占有率
は信号受信処理が約28％、信号及びリレー等の出
力処理が約14％、回線状態監視が約１％程度とみ
なされている。 Therefore, considering the signal output width and pulse interval of the MF signal, it is necessary to scan all lines at a cycle of about 16 mS, and conversely, it is necessary to scan all lines at a cycle of about 16 mS, and conversely, it is necessary to send signals to other stations and monitor the status of line calls, disconnections, etc. Functions and trunk TRK relay control etc. must be considered. Furthermore, in addition to controlling each call path, offline control of input/output devices such as typewriter TYP, printer PTR, display device CRT, etc. is also added, so a central processing unit CPU with higher efficiency is selected in proportion to the increase in call volume. This has a significant impact on the price of the entire system. For example, when configuring a system that uses an existing central processing unit (CPU), the system traffic is
When the processing capacity becomes slightly higher than that of CPU-A (about 10%), the processing capacity of central processing unit CPU-A becomes 1
Central processing unit CPU-B with higher processing power
will be used. However, if the central processing unit CPU-B had 1.5 times the processing power of CPU-A, the current price would be four to five times higher. Specifically, regarding the current call path control function in electronic exchanges, the CPU occupancy rate is approximately 28% for signal reception processing, approximately 14% for signal and relay output processing, and approximately 1% for line status monitoring. ing.
本発明の目的は、電子交換機における通話路制
御に関する信号受信を中央処理装置から独立さ
せ、該処理装置の負荷を軽減した通話路信号処理
方式を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a communication path signal processing system in which reception of signals related to communication path control in an electronic exchange is made independent of a central processing unit, thereby reducing the load on the processing unit.
本発明によれば、信号受信機能を中央処理装置
とは独立なマイクロプロセツサで処理する方式と
することで、処理装置本体の処理能力をカバーし
より経済的なシステムを構成することができる。 According to the present invention, by using a system in which the signal reception function is processed by a microprocessor independent of the central processing unit, it is possible to configure a more economical system that covers the processing capacity of the processing unit itself.
以下、第２図、第３図により本発明の実施例を
説明する。 Embodiments of the present invention will be described below with reference to FIGS. 2 and 3.
第２図は、本発明の概念を示すブロツク図で、
通話路制御装置SPCは公知の信号分配装置SRDの
位置に配置し、中央処理装置CPUとは独立な周
期で自立的に走査装置SCNを起動する。されな
にMF信号を読み取り、全桁数受信と共に中央処
理装置CPUへ起動をかけ、受信データ、回線番
号、受信桁数受信状態の各情報を転送する。 FIG. 2 is a block diagram showing the concept of the present invention.
The communication path control device SPC is placed at the location of the known signal distribution device SRD, and autonomously activates the scanning device SCN at a period independent of the central processing unit CPU. It reads the MF signal, and when all the digits are received, it activates the central processing unit CPU, and transfers the received data, line number, and reception status of the number of received digits.
次に第２図に示す本発明の通話路制御装置SPC
の構成を第３図により説明する。まづ、パルス発
生部TIMから周期パルスが発生するとマイクロ
プログラム制御部SEQでこれを検出する。つづ
いて、マイクロプログラムCMはデータ記憶部ア
ドレスレジスタRARヘアドレスをセツトしデー
タ記憶部RAMから走査装置SCNに収容されてい
る。MF信号読み取りポイント情報を読み出す
と、演算部ALUを経由して走査装置SCNのコマ
ンドレジスタSCRへセツトし、走査装置SCNを
起動する。次に走査装置SCNから読み取りデー
タが返送されると、読み取りデータをアドレスと
して記憶装置RAMの内容を読み出し、演算部
ALUにセツトして、正常受信か否かをチエツク
し回線対応データエリアのアドレスをセツトし該
読み出情報および受信桁数情報を１桁加算しデー
タ記憶部RAMへ書き込む。これら一連の動作を
同一周期内で全回線分終了させる。 Next, the communication path control device SPC of the present invention shown in FIG.
The configuration will be explained with reference to FIG. First, when a periodic pulse is generated from the pulse generator TIM, it is detected by the microprogram controller SEQ. Subsequently, the microprogram CM sets an address in the data storage address register RAR and is stored in the scanning device SCN from the data storage RAM. When the MF signal reading point information is read out, it is set in the command register SCR of the scanning device SCN via the calculation unit ALU, and the scanning device SCN is activated. Next, when the read data is returned from the scanning device SCN, the content of the storage device RAM is read using the read data as an address, and the calculation unit
ALU is set to check whether reception is normal or not, the address of the line corresponding data area is set, the read information and received digit number information are added by one digit, and written to the data storage RAM. These series of operations are completed for all lines within the same cycle.
さらに、次の周期で、ST信号受信の回線があ
れば該当回線の受信データ全てと受信桁数、回線
番号、および受信状態をデータ記憶部RAMから
読み出し、入出力バツフアレジスタＩOＢへセツ
トし、中央処理装置CPUインターフエース制御
部IFCによりプロセツサバスの使用が可能か否か
判断し、可能ならばＩOＢにセツトされたデータ
を中央処理装置CPUへ転送する。 Furthermore, in the next cycle, if there is a line for ST signal reception, all the received data of the corresponding line, the number of received digits, the line number, and the reception status are read from the data storage RAM and set in the input/output buffer register IOB . Then, the central processing unit CPU interface control unit IFC determines whether or not the processor bus can be used, and if possible, transfers the data set in IOB to the central processing unit CPU.
また上記処理中に、中央処理装置CPUより回
線状態監視又は、リレー制御オーダーがあると、
インタフエース装置IFCで検出しMF信号受信処
理の中断アドレスをシーケンサSEQに記憶し中
央処理装置CPUからのコマンドをインタフエー
ス装置IFCにて受信する。しかるのち演算部ALU
にてコマンド演算によりオーダを翻訳し、走査装
置SCN又はリレー駆動回路RCが空きならば、コ
マンドレジスタSCR又はRCRへコマンドをセツ
トし処理命令を実行する。上記中央処理装置
CPUオーダーを終了するとシーケンサーSEQは
記憶されたアドレスを読み出し中断点より動作を
再開する。 Also, during the above processing, if there is a line status monitoring or relay control order from the central processing unit CPU,
The interface device IFC detects and stores the interrupt address of the MF signal reception process in the sequencer SEQ, and the interface device IFC receives a command from the central processing unit CPU. After that, the calculation unit ALU
If the scanning device SCN or relay drive circuit RC is empty, the command is set in the command register SCR or RCR and the processing instruction is executed. Above central processing unit
When the CPU order is completed, the sequencer SEQ reads the stored address and resumes operation from the interrupted point.
以上述べたとおり、本発明によれば、中央処理
装置の負荷を軽減した通話路信号処理方式を実現
することができる。 As described above, according to the present invention, it is possible to realize a communication path signal processing system that reduces the load on the central processing unit.
第１図は従来の通話路信号処理方式図、第２図
は本発明の信号処理方式図、第３図は第２図に示
す通話路制御装置の構成図である。
CPU…中央処理装置、IFC…インターフエス装
置、IOB…入出力バツフアレジスタ、RAM…デ
ータ記憶部、RAR…データ記憶部のアドレスレ
ジスタ、ALU…演算部、RCR，SCR…コマンド
レジスタ、TIM…内部タイミング回路、SEQ…
プログラム制御部（シーケンサ）、CM…マイク
ロプログラム、CMR…マイクロプログラム用レ
ジスタ、DEC…デコーダ。
FIG. 1 is a diagram of a conventional channel signal processing system, FIG. 2 is a diagram of a signal processing system of the present invention, and FIG. 3 is a configuration diagram of the channel control device shown in FIG. 2. CPU...Central processing unit, IFC...Interface device, IOB...I/O buffer register, RAM...Data storage unit, RAR...Address register of data storage unit, ALU...Arithmetic unit, RCR, SCR...Command register, TIM...Internal Timing circuit, SEQ...
Program control unit (sequencer), CM...micro program, CMR...micro program register, DEC...decoder.
Claims (1)
分散して行なう通話路信号処理方式において、 通話路の信号走査装置およびリレー駆動装置と
中央処理装置とに接続した通話路処理装置に、 中央処理装置とは独立した周期のパルスを発生
するパルス発生部と このパルス発生部からの周期パルスを検出する
マイクロプログラム制御部と、 前記信号走査装置に収容されている多周波信号
読み取りポイント情報を記憶するデータ記憶部
と、 この読み取りポイント情報に従つて前記信号走
査装置の起動処理を行う演算部と、 を備え、 前記パルス発生部から周期パルスが発生すると
前記マイクロプログラム制御部はこれを検出し、
つづいてこのマイクロプログラム制御部により前
記データ記憶部から多周波信号読み取りポイント
情報を読み出し、前記演算部の結果に基いて前記
信号走査装置を起動し、 次にこの信号走査装置から読み取りデータが返
送されたとき、ST信号受信の回線があれば該当
回線の受信データ全てと受信桁数、回線番号およ
び受信状態を前記中央処理装置へ転送する ことを特徴とする通話路信号処理方式。[Scope of Claims] 1. In a call path signal processing method in which call path control of an electronic exchange is performed decentrally from a central processing unit, a call path signal processing system connected to a signal scanning device and a relay driving device of the call path and the central processing unit. The apparatus includes a pulse generator that generates pulses with a period independent of the central processing unit, a microprogram control unit that detects the periodic pulses from the pulse generator, and a multi-frequency signal reader housed in the signal scanning device. a data storage unit that stores point information; and a calculation unit that performs startup processing of the signal scanning device according to the read point information, and when a periodic pulse is generated from the pulse generation unit, the microprogram control unit detect,
Next, the microprogram control section reads out the multi-frequency signal reading point information from the data storage section, starts the signal scanning device based on the result of the calculation section, and then returns the read data from the signal scanning device. If there is a line for ST signal reception, all the received data of the line, the number of received digits, the line number, and the reception status are transferred to the central processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11331079A JPS5637791A (en) | 1979-09-04 | 1979-09-04 | Channel signal processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11331079A JPS5637791A (en) | 1979-09-04 | 1979-09-04 | Channel signal processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5637791A JPS5637791A (en) | 1981-04-11 |
| JPS622760B2 true JPS622760B2 (en) | 1987-01-21 |
Family
ID=14608988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11331079A Granted JPS5637791A (en) | 1979-09-04 | 1979-09-04 | Channel signal processing system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5637791A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01129458U (en) * | 1988-02-25 | 1989-09-04 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946894U (en) * | 1972-07-28 | 1974-04-24 |
-
1979
- 1979-09-04 JP JP11331079A patent/JPS5637791A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01129458U (en) * | 1988-02-25 | 1989-09-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5637791A (en) | 1981-04-11 |
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