JPS62276879A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To measure the quality and thickness of a tunneling oxide film at the wafer stage by providing memory cells having tunneling oxide film and floating gate, pads for interconnection, MIS capacitors and interconnections for supplying voltage which is needed for measuring characteristics of the tunneling oxide film. CONSTITUTION:MIS capacitors 3 are formed at least in an area out of pad formation areas for interconnection in a semiconductor integrated circuit and an introduction area 5 of impurities which plays apart of either electrode in the above pad formation areas is connected to pads supplying a negative power source voltage Vss through an extension interconnection 9, while the other electrode 7 is connected to the pads 2 for interconnection through the extension interconnection 8. Under these situations, once an interconnection of the MIS capacitors 3 is made and current/voltage characteristics as well as tension proof are measured at the wafer stage and their data are compared with reference values, actual conditions of tunneling oxide films 6, especially those of tunneling oxide films in the whole memory cells are monitored whether the above date will satisfy intended levels. Thus, such a monitor makes it possible to measure the quality and thickness of the tunneling oxide films at the wafer stage easily and securely.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention provides a semiconductor integrated circuit in which a tunnel oxide film, which is a component of a memory cell, is formed in a part of a region where a wiring pad is formed. By forming an MIS capacitor with the same formed at the same time and by providing actual wiring to supply voltage for measuring the characteristics of the MIS capacitor, it is possible to judge a semiconductor integrated circuit with good performance and durability. The film thickness and film quality of the tunnel oxide film in memory cells, which are important factors in memory cells, can be easily and reliably measured at the wafer stage.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit that requires a tunnel oxide film.

[Conventional technology]

In general, EEPROM (electrical
able and programmable
read only memory) or EEFR
OM and SRAM (static random a
NVRAM (non-volatile memory)
In devices such as RAM (RAM), for example, an MIS transistor having a tunnel oxide film and a floating gate is used as a memory cell, and a tunnel oxide film is formed between the drain and the floating gate. Writing is performed by injecting electrons from the drain to the floating gate, or conversely from the floating gate to the drain.

At that time, electrons tunnel through the tunnel oxide film and reach each electrode.6 (Problem to be solved by the invention) As explained above, the tunnel oxide film is one through which electrons tunnel. Therefore, the uniformity of the film thickness and the quality of the modification have a significant influence on the durability and storage characteristics of the memory cell.

However, in the process of manufacturing such a tunnel oxide film, it is extremely difficult to completely control it, and it is impossible to avoid uneven film thickness and defects in film quality. , while in such a state,
After a memory cell has undergone an erase/write test of about 1000 times, it is required to endure erase/write tests of about 10' to 105 times.

In order to solve this problem, it is possible to check the reliability by performing a test of about 104 to 105 times by sampling each loft, but this is extremely difficult at the wafer stage in the mass production process. It is a difficult task.

The reason for this is that it is difficult to keep the probe in good contact with the wafer for a long period of time, and for example, if one erase/write requires 5 (ms), 1000 times requires 5 (ms). (S) Therefore, the upper limit of the erase/write test that can be performed on one chip is about 2000 times at most due to the probe contact problem and the test time. Therefore, after performing an erase/write test on all chips ~2,000 times to distinguish between good and defective products in advance, some chips were selected from the group of good products that passed the test and tested 104 to 105 times. If the durability of the entire lot is to be guaranteed by erasing/writing, the test will take a very long time, which will lengthen the process itself and increase costs.

The present invention provides a semiconductor integrated circuit configured so that the thickness and quality of the tunnel oxide film can be monitored in the wafer state, thereby making it possible to easily and reliably eliminate defective products at the wafer stage.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, a memory cell formed in a semiconductor chip (for example, semiconductor chip 1) and having a tunnel oxide film and a floating gate, and a semiconductor chip in which the memory cell is formed, Wiring pads (for example, wiring pads 2) arranged around the periphery, and MrS capacitors (for example, MIS capacitors 3) having the pads located in the formation area of the wiring pads and formed at the same time as the tunnel oxide film; The configuration includes wires (for example, lead wires 8 and 9) for supplying voltage in order to measure the characteristics of the tunnel oxide film in the M+s capacitor.

[Effect]

By adopting the above method, the thickness and quality of the tunnel oxide film in the memory cell, which is an important factor in determining whether the performance and durability of the semiconductor integrated circuit are good, can be evaluated on the wafer. It can be easily and reliably measured in stages.

〔Example〕

FIG. 1 shows a plan view of essential parts of an embodiment of the present invention.

In the figure, 1 is a semiconductor chip, 2 is a wiring pad, and 3 is a semiconductor chip.
is an MIS capacitor using tunnel oxide film, 3A is M
Wiring connecting the IS capacitor and the wiring pad is shown.

FIG. 2 shows a cutaway side view of the main part of the MIS capacitor part seen in FIG. 1.

In the figure, 4 is a silicon semiconductor substrate, 5 is an impurity doped region that becomes one electrode of the MIS capacitor, 6 is a tunnel oxide film, 7 is the other electrode of the MIS capacitor, and 8 is a wiring pad. Reference numeral 9 denotes a lead wire connected to a pad to which a voltage test voltage VTEST (for example, 13 [V]) is applied, and a lead wire 9 connected to a pad that supplies, for example, a negative power supply voltage VSS. Incidentally, the tunnel oxide film 6 is, of course, formed at the same time as the tunnel oxide films for forming other memory cells.

In the present invention, as shown in the illustrated example, M
An impurity-doped region 5 that forms the IS capacitor 3 and serves as one electrode thereof is connected to a pad (not shown) that supplies a negative power supply voltage VSS via an extraction wiring 9, and the other The electrode 7 is connected to the wiring pad 2 via a lead wiring 8. Note that the lead wire 9 of the impurity region 5 may be left independent without being connected to the pad for the negative power supply voltage VSS.

In this way, the MIS capacitor 3 is actually wired, and the current-voltage characteristics and breakdown voltage are measured in a test at the wafer stage and compared with standard values to determine the quality of the tunnel oxide film 6 and, therefore, the overall memory cell. Monitor the quality of the tunnel oxide film. When the measurement is completed, a voltage higher than the nominal withstand voltage is gradually applied to the MIS capacitor 3 to destroy it.
Knowing the maximum withstand voltage is optional.

Since the MIS capacitors 3 as described above are provided on all chips within the wafer, by measuring them and analyzing the average and deviation, it is possible to determine the tunnel oxide film within the wafer. Since the distribution of film thickness and film quality can be easily and reliably determined, and Roso I-evaluation can be performed in the same way, it is also possible to determine the loft for shipping.

〔Effect of the invention〕

In the semiconductor integrated circuit according to the present invention, a MIS capacitor having a tunnel oxide film which is a constituent element of a memory cell is formed in a part of the wiring hatch formation region, and the MIS capacitor is The configuration is such that the actual wiring is used to supply the voltage for measuring the characteristics of the device.

By adopting the above configuration, the I1g thickness and film quality of the tunnel oxide film in the memory cell, which are important factors in determining whether the performance and durability of the semiconductor integrated circuit are good, can be determined on the wafer. It can be easily and reliably measured in stages.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of an embodiment of the present invention, and FIG. 2 is a cutaway side view of the main part. In the figure, 1 is a semiconductor chip, 2 is a wiring pad, and 3 is a semiconductor chip.
is an MIS capacitor using tunnel oxide film, 3A is M
Wiring connecting the IS capacitor and the wiring pad, 4 is a silicon semiconductor substrate, 5 is an impurity-introduced region that becomes one electrode in the MIS capacitor, 6 is a tunnel oxide film, 7 is the other electrode in the MIS capacitor, Reference numeral 8 designates a lead wire connected to a wiring pad to which a tunnel film test voltage VTESA (for example, 13 [V]) is applied; 9 designates a lead wire connected to a pad that supplies, for example, a negative side type a voltage VSS. are shown respectively. Fig. 1 Plan view of main parts of the embodiment

Claims (1)

[Scope of Claims] A memory cell formed in a semiconductor chip and having a tunnel oxide film and a floating gate; Wiring pads arranged around the semiconductor chip in which the memory cell is formed; and the wiring. an MIS capacitor formed at the same time as the tunnel oxide film in a region where the tunnel oxide film is formed, and wiring for supplying a voltage to measure the characteristics of the tunnel oxide film in the MIS capacitor. A semiconductor integrated circuit characterized by: