JPS62283761A - data receiving device - Google Patents

Abstract

PURPOSE:To exactly identify a binary signal and a tonal signal by interrupting a reception of the tonal signal under a prescribed condition, and thereafter, executing a reception of the binary signal. CONSTITUTION:The titled device is provided with a control means A for interrupting a reception of a tonal signal under a prescribed condition, and executing a binary signal. For instance, the control means A interrupts a reception of the tonal signal, when at least (n) pieces of prescribed flag patterns have been detected, and executes control so that only the reception of the binary signal is executed. Or this control means A can also execute the control so that the reception of the tonal signal is interrupted, when a signal cut-off state has been detected, and only the reception of the binary signal is executed. In this way, it does not occur that it is misconceived that the tonal signal has been received, in spite of a fact that the binary signal has been received.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data receiving device having a function of receiving binary signals and tonal signals.

[Prior Art] Facsimile machines have been widely known as this type of data receiving device. Among these facsimile machines, a facsimile machine having both G2 and G3 afl needs to receive either a binary signal or a tonal signal sent from one communication partner in the pre-procedure.

That is, when a conventional facsimile machine is in a transmitting state, Dis (Digital Identifica
Binary signals such as tion Signa L: Digital identification signal or GI (Group Ident signal)
First, a tonal signal such as a loop identification (identification) is received.

When a binary signal is received, CCIT'T Recommendation G3 transmission operation is performed according to the procedure based on the binary signal.Here, the binary signal rQJ is 1850Hz.
, "1" is represented by 1850Hz.

On the other hand, among the tonal signals, a 1850 Hz signal that continues for 1.5 seconds is used for the GII signal, and a 1850 Hz signal that continues for 1.5 seconds is used for the CI2 signal.

However, with traditional facsimile machines.

When receiving either a tonal signal or a binary signal, the reception of the tonal or binary signal was not interrupted.

As a result, in the first command receiving operation on the transmitter side, the initial identification signal (NSF signal/C9I signal/DI!J signal) of the binary signal sent from the receiver side is used as the group identification signal (DI signal) of the tonal signal. ) was sometimes mistaken.

Therefore, depending on the timing at which reception of NSF/CSI/DIS signals and the like is started, it is possible that a binary signal may be mistakenly recognized as being received as a tonal signal. Further, if noise or the like occurs in a no-signal section, it may be mistaken for reception of a tonal signal.

[Problems to be Solved by the Invention] As described above, it has been observed that the conventional data receiving device incorrectly discriminates between a binary signal and a tonal signal, causing trouble in communication control.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide a data receiving apparatus configured to accurately discriminate between a binary signal and a tonal signal under any transmission conditions.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for receiving tonal signals under predetermined conditions in a data receiving device equipped with a moat for receiving binary signals and tonal signals. control means for interrupting the operation and receiving the binary signal.

[Operation] By interrupting the reception of the tonal signal under a certain predetermined condition and then receiving the binary signal, the system operates to prevent erroneously identifying the two.

[Embodiment] Fig. 1 is an overall configuration diagram of a facsimile apparatus to which the present invention is applied. For example, when the control means A included in the apparatus detects at least n predetermined flag patterns, the control means A interrupts the reception of the tonal signal and performs control to only receive the binary signal, or performs this control. When the means A detects a signal cut-off state, it is also possible to control the apparatus so that the reception of the tonal signal is interrupted and only the reception of the binary signal is performed.

FIG. 2 is a block diagram showing an embodiment of a facsimile apparatus to which the present invention is applied.

In FIG. 2, 2 is a network control unit NCU (Nat-
Since the telephone network is used for data communication, etc., it connects to the terminal of the line and performs functions such as controlling the connection of the telephone switching network and switching to a data communication path. In addition, the signal line 2a
is a telephone line. This NC 112 manually outputs a signal on the signal line 38a, and if this signal level is "0", the telephone line is connected to the telephone side (that is, the signal line 2a is connected to the signal line 2b).
Connect to. Further, a signal on the signal line 38a is input, and if the signal level is "1", the telephone line is connected to the facsimile machine side (that is, the signal line 2a is connected to the signal line 2c). Under normal conditions, the telephone line is connected to the telephone side.

4 is a telephone.

6 is a hybrid circuit that separates a transmission system signal and a reception system signal. That is, the transmission signal on the signal line 18a is sent out to the telephone line via the signal line 2C and NCu2. Also, the signals sent from the other party are sent to the NCU.
2 and signal line 2C, and is output to signal line 6a.

Reference numeral 8 denotes a reading circuit which sequentially reads image signals for one line in the main scanning direction from the original to be transmitted, and creates a signal string representing binary values of white and black. This reading circuit 8 is COD'
It consists of an imaging device such as a charge-coupled device (charge coupled device) and an optical system. Further, the signal string that has been binarized into white and black is output to the signal line 8a.

10 is an encoding circuit. This encoding circuit 10 inputs the binarized signal output to the signal line 8a,
The data is encoded (MW (Modified Huffman) encoding or MR (Modified Read) encoding), and the encoded data is output to the signal line 10a.

Reference numeral 12 denotes a modulator that modulates the known C based on ITT recommendation V27ter (differential phase modulation) or V29 (orthogonal modulation a). This modulator 12 manually modulates the signal on the signal line 10a, and transmits the modulated data to the signal line 12a.
Output to.

14 is a parallel-serial (P/S) conversion circuit. This parallel-serial conversion circuit 14 has two buffers (buffer "0" and buffer "1"). At the beginning, both buffers are empty, so a byte pack clock is generated on the signal line 14a. Then, when byte data is written from the control circuit 38, this data is stored in buffer "0". The data stored in buffer "O" is moved to buffer 1 since the other buffer (buffer "1") is empty. Then, since the buffer "0" becomes empty, a byte pack clock is generated on the signal line 14a. Then, when byte data is written from the control circuit 38, this data is stored in buffer "0". Byte data sent from the control circuit 38 is written into this buffer via the signal line 38b. This P/S conversion circuit 14 performs parallel-to-serial conversion on the byte data stored in the buffer "1", and outputs serial data to the signal line 14b every time a clock is sent to the signal line 16a. When 8-bit serial data is output to the signal line 144),
Since buffer "1" becomes empty, the byte data stored in buffer "0" is transferred to buffer "1". Then, a byte pack clock is generated on the signal line 14a. When byte data is written from the control circuit 38 via the signal line 38b, this data is stored in the buffer "O".

Each time the byte pack clock is sent to the signal line 14a, the procedure signal is byte packed and sent to the signal 9i1:18b.

・16 is a modulator that performs modulation based on the well-known C(:ITT recommendation V21). This modulator 16 outputs a clock representing the data transmission timing to the signal line 1δa. The serial procedure signal on the signal line 14b is input and modulated, and the modulated data is output to the signal line 16b.

17 is a GI2 signal sending circuit. This circuit 17 is
When a pulse is generated on the signal line 38c, a G signal is applied to the signal line 17a.
Sends I2 signal. Further, when the transmission of the GI2 signal is completed, 18 which generates a pulse on the signal line 17b is an adder circuit. This adder circuit 18 inputs the signals of the signal line 12a, the signal line 16b, and the signal line 17a, and outputs the added result to the signal line 18a.

20 is a demodulator that performs demodulation based on the well-known CITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation).The demodulator 20 inputs the signal on the signal line 6a and performs demodulation. and outputs the demodulated data to the signal line 20a.

22 manually decodes the demodulated data output to the signal line 20a and decodes it (M)I (Modified Huffman).
This circuit outputs decoded or MR (modified read) decoded data to the signal line 22a.

24 is a recording circuit that manually inputs the decoded data output to the signal line 22a and records white and black signals line by line.

Reference numeral 26 denotes a demodulator that performs demodulation based on the well-known CITT recommendation V21. 1.-The timing clock for each day is output to the signal line 26a.

28 is a serial-parallel (S/P) conversion circuit. When the clock is sent to the signal line 26a eight times, 8 bits of data are collected (this data is the signal output to the signal line 28b), so when the 8 bits of data are collected, the serial-parallel The conversion circuit 28 generates a clock on the signal line 28a and transfers the byte data to the signal line 28a.
Output to 8b.

30 is an amplifier that inputs and amplifies the signal of the signal line 6a. The amplified signal is output to the signal line 30a.

That is, since the signal sent from the other party's facsimile machine is attenuated by the telephone line, which is the transmission medium, before reaching the facsimile machine, the signal is amplified by the amplifier 30.

32 is a binarization circuit that manually inputs the signal of the signal line 30a and binarizes it with respect to a certain reference voltage. The binarized signal is output to the signal line 32a.

34 is a tonal counter which inputs the signal of the signal line 32a and measures the time of one cycle of the signal. This one cycle time allows the frequency of the received signal to be recognized. This tonal counter is used to recognize the frequency of the signal sent to the line by the other party's facsimile machine.

FIG. 3 is a waveform diagram showing the signal on the signal line 6a and the binarized signal on the signal line 32a. Here, the binarized signal is further frequency-divided, the time of one period T is measured,
The frequency is then determined. As a method of measuring one period T, a certain clock (in this example, 77
．． 78kHz). In this case, for example, a 2100 Hz signal corresponds to 37 clocks. That is, when the number of clocks for one period is between 35 and 39, it is determined that the frequency of the signal is 2100 Hz. Here, 35 clocks correspond to 2222H2, and 39 clocks correspond to 1994Hz. In this way, 1994Hz to 2222H
When a signal of z is detected, it is assumed that a signal with one period of 2100 Hz is detected.

Then, within a certain period of time, the time of one cycle is 2100.
Hz (the number of clocks is 35 to 39) is detected multiple times, it is determined that a signal of 210011z has been detected.

When one period of measurement is completed, the tonal counter circuit 34 generates a pulse on the signal line 34a and also outputs a pulse on the signal line 34a.
4b outputs data indicating how many locks there are.

36 is a signal presence/absence detection circuit which inputs the signal of the signal line 6a, and outputs a signal of signal level "1" to the signal line 36a when a signal of -43 dBm or more is detected, and -
When a signal of 48 dBm or less is detected, signal line 36
A signal with signal level "0" is output to a. Further, when the signal on the signal line 6a is more than -48 dBm and less than -43 dBm, there is no signal on the signal line 36a.

No. a of level "0" or signal level "1" is output.

38 is a control circuit that performs the control described below. Here, two cases will be considered as aspects of the signal sent from the other party's facsimile machine.

Below, the explanation will be divided into two parts: control (1) and control (2).

Control ■: When this sofa fax machine is on the image receiving side, it first sends an initial identification signal and then receives the signal sent from the other party's facsimile machine. be.

Control (2): When the facsimile machine is the image transmitting side, it first receives the initial identification signal sent from the other party's facsimile machine, and this is the control for receiving the signal in this case.

The above-mentioned control (2) will be explained below with reference to the flowchart shown in FIG.

In FIG. 4, step 550 shows processing when receiving an image.

In step S52, the timer T1 is set to 35 seconds.

In step S54, (GI2. Group identification)
NSF, non-standard equipment/C51, called station identification/[+1
5. Sends out a digital identification signal. Here, the GI2 signal is not sent the first time, but is sent from the second time.

In step S56, the timer T4 is set to 3 seconds or 4.5 seconds. Here, in the case of self-excited reception, set the timer T4 to 3 seconds, and in the case of manual reception,
Set timer T4 to 4.5 seconds.

In step 558, it is determined whether a CCITT Recommendation V2 Recommendation Type 21 signal has been received.

If the CCITT Recommendation V2 Recommendation Type 21 Lee signal is received, the process proceeds to step 560. When the CCITT Recommendation V2 Recommendation 21 Lee signal is not received, step S62
Proceed to.

Step S6G represents transition to the G3 mode binary procedure.

In step S62, the GC2 signal or the PI
It is determined whether the S (procedure interruption) signal is detected.

When detecting GC2 signal or PIS signal,
The process advances to step S64. If no GC2 signal or PIS signal is detected, the process advances to step 566.

Step S64 represents transition to a tonal procedure. The facsimile machine according to this embodiment is C1l:
77-gun Recommendation G2. G3. Since it is assumed that the function exists, the GC2 signal and the PI
Receives the S signal. Here, when the GC2 signal is received, transmission is performed in the G2 mode, and when the PIS signal is received, the process proceeds to the telephone mode.

In step 56B, it is determined whether timer T4 has timed out. When timer T4 times out, the process proceeds to step 568. If the timer T4 has not timed out, the process advances to step 558.

In step 568, it is determined whether timer T1 has timed out. When the timer TI times out, the process proceeds to step 570. If the timer T1 has not timed out, the process advances to step S54.

In step 570, the DCN (disconnect command)
Sends signals.

Step 572 represents line disconnection.

In the schematic flowchart shown in FIG. 4, functions unique to this embodiment are not shown.

Next, the details of the control procedure according to this embodiment are shown in FIG.
This will be explained with reference to (5).

In FIG. 5, step S80 represents processing on the image receiving side.

In step S82, the telephone line is connected to the facsimile machine. Specifically, a signal of signal level "1" is output to the signal line 38a.

In step S84, 5IGTRC(SIGNA
LTRNC0NTR0L) Set the flag to "0".

Step 58B waits for 2 seconds.

In step 588, it is determined whether or not the reception is automatic. If it is automatic reception, the process advances to step S90. If it is manual reception, the process advances to step S94.

In step S90, a CHD (called station identification) signal is sent.

In step S92, T4SAV is set to 3 seconds.

In step 594, TJSAV is set to 4.5 seconds.

In step 596, timer T1 is set to 35 seconds.

In step 598, flag 5IGTRC is set to “O
” is determined. Here, when transmitting the initial identification signal, control is performed such that the GI2 signal is not transmitted only the first time. When flag 5IGTRC is "0", the process advances to step 5102. Also, flag 5 IGTRC
is not "0", the process advances to step 10G.

In step 5100, the GI2 signal is sent.

Specifically, it generates a pulse on the signal line 38c, starts sending out the GI2 signal, and waits for a pulse to be generated on the signal line 17b. When a pulse is generated on the signal line 17b, the process advances to step 5104.

In step 5102, flag 5IGTRC is set to 1.
Set.

In step 5IQ4, NSF -C5I -
Sends 0l5 signal. Specifically, by sending byte data to the signal line 38b every time a pulse is generated on the signal line 14a, the NSF-CSI-[11S signal is sent, and the last flag is one.

In step 5106, the time stored in T4SAV is set in timer T4.

In step 5108, OOH is set in the area BIR(O) in which the received data is stored.

In step 5110, OOH is set in the area BIRCI in which the received data is stored.

In step 5112, the echo timer ECII
Set 600m5 to TIM.

In step 5114, two consecutive bytes of 7EH
(01111110B) “1” when a pattern is detected
The flag FLGIDT, which is set to ``O'', is set to ``O''.

In step 5116, the flag FLGDET is set to “
0”.

In step 5118, a counter CNTBY is used to count the number of bytes when receiving one frame.
Set "0" to T.

In step 5120, when the frequency of one cycle of the signal is analyzed and it is determined that it is 2100 Hz 788 times, it is determined that the GC2 signal has been detected. 788 is set in the counter CNT210 used to count these 788 times. 1 every 2 cycles
It is possible to analyze the frequency 788 times.
The total number of times is 788 X - x 2 = 0.75 seconds 21Q
This corresponds to detecting QHz.

In step 5122, when the frequency of one period of the signal is analyzed, it is determined that it is 462H1.
If there are 31 times, it is determined that the PIS signal has been detected. The counter CNT462 used to count these 231 times is set to 231. Since it is possible to analyze the frequency once every two periods, 231 times is
Total 231 x - x 2 = 462H for 1.00 seconds
Corresponds to detecting z.

In step 5124, it is determined whether a 300 b/s byte clock has occurred. in particular,
It is determined whether a clock is generated on the signal line 28a. If a byte clock of 300 b/s occurs (that is, when a clock is generated on the signal line 28a), the process proceeds to step 5160. ), the process proceeds to step 5126.

In step 5126, FLGf1)T is "0"
In other words, it is determined whether or not a continuous 2-byte flag pattern (7EH) is detected. FL
When GIDT is "0", that is, when a continuous 2-byte flag pattern (7E1) is not detected,
Proceed to step 5128. When FLGIDT is “1”, that is, a 2-byte continuous flag pattern (7E
If the old signal is detected, the process advances to step 5150 and no analysis of the tonal signal is performed.

In step 3128, SE+)(Signal
It is determined whether EnergyDetect) is 1, that is, whether the signal level of the signal line 36a is "1". When SED is 1, that is, signal line 3
When signal level 8a is "1", step! ! 13
0 and proceed to the analysis of the tonal signal. SED is “O”
In other words, when the signal line 35a is at the signal level "O"
If so, the process advances to step 5150 and no analysis of the tonal signal is performed.

Steps 5126 and 5128 above represent parts unique to this embodiment.

In step 5130, it is determined whether or not the analysis of one cycle of the tonal signal has been completed, that is, whether or not a pulse has been generated on the signal line 34a.

When the analysis of one period of the tonal signal is completed, that is, when a pulse is generated on the signal line 34a, the process advances to step 5132. Further, if the analysis of one period of the tonal signal has not been completed, that is, if no pulse is generated on the signal line 34a, the process advances to step 5150.

In step 5132, the tonal data (ie, the signal on the signal line 34b) is input manually.

In step 5134, it is determined whether the currently received one-cycle signal is 2100 Hz. If the received one-cycle signal is now 2100 Hz, the process advances to step 5136. The signal of one period received now is 210
If it is not 011z, the process advances to step 5142.

In step 5136, the value of counter CNT210 is decremented by one.

In step 5138, it is determined whether the value of counter CNT210 is negative, that is, whether the GC2 signal has been detected. When the value of counter CNT210 is negative, that is, when the GC2 signal is detected, the process advances to step 5140. When the value of counter GNT210 is positive or zero, that is, when the GC2 signal is not detected, the process advances to step 5150.

Step 5140 indicates that it is determined that the GC2 signal has been received and that the mode is shifted to the G2 reception mode.

In step 5142, it is determined whether the currently received one-cycle signal is 462H2. If the received one-cycle signal is 462Hz, step 51
Proceed to step 44. The signal of one period received now is 462 tlz
If not, proceed to step 5150.

In step 5144, the value of counter CNT462 is decremented by one.

In step 5146, it is determined whether the value of counter CNT462 is negative, that is, whether the PIS signal has been detected. When the value of counter CNT462 is negative, that is, when the PIS signal is detected, the process advances to step 5148. When the value of counter CNT462 is positive or zero, that is, when the I'lS signal is not detected, the process proceeds to step 5150.

Step 5148 represents determining that a PIS signal has been received and transitioning to telephone mode.

In step 5150, it is determined whether timer T1 has timed out. When the timer T1 times out, the process advances to step 5154. Timer T
1 has not timed out, step 51
Proceed to step 52.

In step 5152, it is determined whether timer T4 has timed out. When the timer T4 times out, the process proceeds to step 598. Timer T4
has not timed out, step 512
Proceed to step 4.

In step 5154, the DCN (disconnect command)
Send a signal. Specifically, the DCN signal is sent by sending byte data to the signal line 38b every time a pulse is generated on the signal line 14a. The last flag is one.

In step 5156, the telephone line is connected to the telephone side. Specifically, the signal level "1" is applied to the signal line 38a.
Outputs the signal.

Step 3158 represents an off state.

In step 5160, the echo timer EC)I
Whether TIM has timed out or not, i.e. (GI
2) ・NSF - (: After sending the 5I-0I5 signal,
It is determined whether 60 Gms has elapsed. If the echo timer ECIITIM times out, that is, if Booms has elapsed after sending the (GI2) - NSF-CSI-0I5 signal, the process proceeds to step 5162 and a binary signal is received. On the other hand,
Echo timer EC) If ITIM has not timed out, that is, (GI2) ・N5F-C5I
- If 600 m5 has not elapsed since the DIS signal was sent, the process advances to step 5126 and a tonal signal is received. This means that when your own aircraft sends a signal and receives signals sent from the other machine, reception of tonal signals begins immediately, and reception of binary signals begins after a certain period of time has elapsed. It shows. This is a part unique to this embodiment. As a result, no malfunction will occur for echoes of 600 m5 or less.

In step 51B2, the received binary data (that is, the data on the signal line 28b) is transferred to the memory BIR.
Store in C2.

In step 5164, a counter IITTCτ for counting the received binary data (8 bits) is set.
Set 8 to 1.

In step 5166, it is determined whether the value of memory o+nco is 7CI+ (ie, flag pattern). When the value of memory B[RCO is 7EH (ie, flag pattern), the process advances to step 5168. If the value of the memory BIRCO is not 7EH (ie, flag pattern), the process advances to step 5174.

In step 5168, the flag FLGIDT is set to 0.
It is determined whether or not. When the flag FLGIDT is 0, that is, when the 2-byte consecutive 7EI ((flag pattern) is not detected, the process advances to step 5170. When the flag FLGIDT is not 0, that is, when the 2-byte consecutive 7EI((flag pattern) pattern) is being detected, the process advances to step 5180.

In step 5170, it is determined whether the value of memory BIIICI is 7εH (ie, flag pattern). When the value of memory BIRCI is 7Ell (ie, flag pattern), the process advances to step 5172. If the value of memory BIRCI is not 7EH (ie, flag pattern), the process advances to step 5174.

In step 5172, two consecutive bytes of 7E
Since l+ (flag) pattern was detected, flag FLG
Set IDT to "1".

In step 5174, it is determined whether the counter BITCTI is "0", that is, whether all byte data checks manually performed in step 5162 have been completed. When the counter BITCTI is "O", that is, when all the byte data input in step 5162 have been checked, the process advances to step 5184. On the other hand, if the counter BITCTl is not r□, that is, if all the byte data manually checked in step 5162 has not been completed, the process advances to 5176.

In step 5176, memory [l[RC2,B
IRCI.

Move the BIRCO data 8 bits to the right. This situation is illustrated in FIG.

In step 5178, the value of counter BITCTI is decremented by one.

In step 5tao, it is determined whether the value of the memory BIRC1 is 7EI+ (ie, a flag pattern). When the value of the memory BIIICI is 7EH (ie, flag pattern), it is determined that the flag pattern is continuous, and the process advances to step 5174. If the value of memory [1111(:1) is not 7E)I (ie, flag pattern), it is determined that the transmission of the preamble has been completed, and the process proceeds to step 5182.

In step 5182, the flag FLGDET indicating that the last flag of the preamble has been detected is set to "1".
”.

In step 5184, the flag FLGDET is set to “
0'', that is, whether or not the last flag of the preamble has been detected. Flag F1.
When GDET is "0", that is, when the last flag of the preamble has not been detected, step 512B
Proceed to. On the other hand, when the flag FLGDET is "1",
That is, when the last flag of the preamble is detected, the process advances to step 5186.

The process proceeds to step 518B when a continuous flag pattern of 2 or more bytes is detected, and then a pattern other than the flag pattern is detected.

Here, the final part of the binary signal sent by the machine itself has one flag. Therefore, the flag of the final part of the binary signal sent by the own machine is not detected and the process does not proceed to step 5186.

Ha D -F Your HIAI L ÷ Ba, / -) --I
I I Rei Lu's no? ' Do 4. That is, 300b/s
Each time a byte clock (byte clock of signal line 28a) is generated, byte data is input, and the byte data is written into the memory while calculating 0 delete and FC5.

The number of bytes received is shown in counter CNT[lYT. Here, when the timer Tl times out while receiving a binary signal, a DCN (disconnection command) signal is sent, and then the telephone line is connected to the telephone side and turned off.
becomes. Further, when the flag of the final portion is detected, the process advances to step 5188. 200 while receiving binary signal
If it is detected that CD (carrier detect) is "0" continuously for ms, the process advances to step 5108.

Furthermore, the number of bytes in one frame ([:NTOYT) is 12
If the number exceeds 8, the process also proceeds to step 5108. this is,
This is a function unique to this embodiment. Here, the counter BIT
It also controls CTI, etc.

In step 5188, it is determined whether the number of bytes (CNTBYT) of the currently received frame is less than five. If the number of bytes in the received frame is less than 5, the process advances to step 5108. Also, if the number of bytes of the received frame is 5 or more, step 5190
Proceed to. Here, the number of bytes when correctly receiving the binary signal is at least 5 bytes (address, control, facsimile control, facsimile information field, frame check sequence 2 bytes).

In step 5190, it is determined whether the frame check sequence is correct. If the frame check sequence is correct, proceed to step 5192. If the frame check sequence is incorrect, step 5
Proceed to step 108.

In step 5192, the facsimile information field of the received binary signal is analyzed.

In step 5194, the binary code just received is
It is determined whether the data is a CRP (command retransmission request) signal. If the binary data just received is a CRP signal, the process advances to step 5210. Also, if the binary data just received is not a CRP signal, step 5
Proceed to 196.

In step 5196, it is determined whether the currently received frame is the last frame.

If the currently received frame is the last frame, the process advances to step 5198. Further, if the currently received frame is not the last frame, the process advances to step 5206.

In step 5198, it is determined whether the currently received binary signal is the same as the previously sent binary signal. If the binary signal just received is the same as the binary signal sent out immediately before, the process advances to step 5200. Further, if the binary signal just received is different from the binary signal sent immediately before, step 52
Proceed to step 12.

In step 5200, it is determined whether the binary signal just received is a Dis (digital identification signal) signal. Further, if the binary signal just received is a D■S signal, the process advances to step 5202. Furthermore, if the binary signal just received is not a DTS signal, it is determined to be an echo and the process proceeds to step 5108.

In step 5202, it is determined whether or not the call is automatically received. If the call is not automatically received, the process advances to step 5204. When the call is automatically received, detecting the DIS group signal is meaningless, so step 5108
Proceed to.

In step 5204, it is determined whether the PIF (facsimile information field) of the binary signal sent just before and the binary signal just received are the same. If the PIF of the binary signal sent just before and the binary signal just received are different, the process advances to step 5212. Also, if the PIF of the binary signal sent just before and the binary signal just received are the same, it is judged as an echo,
Proceed to step 5108.

Steps 519B to 5204 are measures against echo. This is a feature unique to this embodiment.

In step 5206, the flag FLGDET is set to “
Set "O".

In step 5208, the flag CNTBYT is set to “
0”.

In step 5210, a step 52, which will be described later,
V21 signal CD showing 12 to 5240km steps
After confirming that =0, the process advances to step 598.

In step 5212, timer T2 is set to 10 seconds.

In step 5214, memory BIRCO is 7E
It is determined whether the pattern is H (flag pattern). Memory B [When RCO is 7EH (flag pattern), proceed to step 5216. Also, memory [1IItC
If O is not 7EI+ (flag pattern), the process advances to step 5218.

In step 5216, it is determined whether the memory is [1tllCI or 7E11 (flag pattern). When memory B[RC1 is 7EH (flag pattern), it is determined that the flag signals are continuous, and the process advances to step 5218. Also, memory BIRCI h) 7E
Not H (flag pattern) (Memory BIIICO is 7
If it is E11 (flag pattern), it is determined that a closed flag has been detected, and the process proceeds to step 5236.

In step 5218, it is determined whether the counter BITCTI is "O". Counter 81TCT
If 1 is "0", the process advances to step 5224. Further, when the counter BITCTI is not "0", the process advances to step 5220.

In step 5220, the memory 811'([:2
．． BIRCI.

Move the data in Bin(O 8 bits to the right.

In step 5222, the value of counter BITCτl is decreased by 1.

In step 5224, it is determined whether timer T2 has timed out. When timer T2 times out, the process advances to step 5232.

On the other hand, when timer T2 has not timed out,
Proceed to step 3226.

In step 522B, it is determined whether a 300 b/s byte clock has been generated, that is, whether a clock has been generated on the signal lR2Ba.

When a byte clock of 300b/s occurs, that is, when a clock is generated on the signal line 28a, step 5 is executed.
Proceed to 228. Further, when the byte clock of 300b/S is not generated, that is, when the clock is not generated on the signal line 28a, the process advances to step 5224.

In step 5228, the received binary data (data output to the signal line 28b) is transferred to the memory BI.
Store in llC2.

In step 5230, a counter 8ITCTl is set to 8.

In step 5232, the telephone line is connected to the telephone set. Specifically, the signal level r O is applied to the signal line 38a.
Outputs the J signal.

Step 5234 represents an error.

In step 5236, timer T2 is set to 1 second.

In step 5238, the S
It is determined whether ED (Signal Energy Detect) is detected to be "0". Whether this SED is “0” or “1” is determined by the signal line 36.
The signal of a is judged manually. S continuously for 200m5
When it is detected that ED is "0", step 52
Proceed to step 42. Further, if it is not detected that SED is "O" continuously for 20OfflS, step 52
Proceed to 40.

In step 5240, it is determined whether timer T2 has timed out. When timer T2 times out, the process advances to step 5242. On the other hand, if timer T2 has not timed out, step 5
Proceed to 238.

Steps 5212 to 5240 indicate functions unique to this embodiment.

Step 5242 represents that the reception of the binary signal to 300b is completed and the process proceeds to the next operation based on the received signal.

In FIG. 5 mentioned above, when a bite crotch of 300 b/s occurs (determined in step 5L24), 3
00b/s analysis. When the 300b/S analysis does not determine that a binary signal is being received,
Proceed to step 512B.

Furthermore, when the analysis of one cycle of the tonal signal is completed (determined in step 5130), the process proceeds to the analysis of the tonal signal.

In the analysis of the tonal signal, if it is determined that no tonal signal has been received, the process advances to step 5124.

In this way, when it is necessary to receive tonal and binary signals simultaneously, it is possible to always receive tonal and binary signals without overlooking all the received signals. This is a feature unique to this embodiment.

Next, the above-mentioned control (2) will be explained with reference to the flowchart shown in FIG.

In FIG. 7, step 5250 represents processing on the image sending side.

In step 5252, timer TI is set to 35 seconds.

In step 5254, it is determined whether a binary signal of CCTTT Recommendation V21 has been received.

[:(: If the binary signal of ITT Recommendation V21 is received, the process proceeds to step 5256. If the CCITT recommendation V2 recommendation type 21 signal is not received, the process proceeds to step 5258.

Step 5256 represents transition to G3 mode binary procedure.

In step 5258, it is determined whether the GI2 signal is detected. When the GI2 signal is detected, the process advances to step 5260. On the other hand, if the GI2 signal is not detected, the process advances to step 5262.

Step 5260 represents transition to a tonal procedure. The facsimile machine according to this embodiment is C(:
ITT Recommendation G2. Since it is assumed that the device has the G3 function, it is necessary to receive the GI2 signal as the tonal signal.

In step 5262, it is determined whether timer T1 has timed out. When the timer TI times out, the process advances to step 5264. Also, when the timer Tl has not timed out,
Proceed to step 5254.

Step 5264 represents line disconnection.

In the above-described schematic flowchart shown in FIG. 7, functions unique to this embodiment are not shown. So, Figure 8 (
Referring to the detailed flowcharts shown in 1) to (4),
The control procedure of this embodiment will be described.

In FIG. 8, step 5270 represents processing on the image sending side.

In step 5272, the telephone line is connected to the facsimile machine. Specifically, a signal of signal level "1" is output to the signal line 38a.

In step 5274, the timer Tl is set to 35 seconds.

In step 5276, the counter GI2DET for counting how many times the GI2 signal is detected is set to "0".
”.

In step 5278, OOH is set in area BII1GO for storing the received data.

In step 5280, 0011 is set in area BInCI for storing the received data.

In step 5282, two consecutive bytes of 7EH
The flag FLGIDT, which is set to ``1'' when a <flag pattern) is detected, is set to ``0''.

In step 5284, the flag FLGDET is set to “
0”.

In step 5285, a counter CN is used to count the number of bytes when receiving one frame.
Set TBYT to “0”.

In step 5288, when the frequency of one period of the signal is analyzed, if it is determined that it is 1850H1 463 times, it is determined that one GI2 signal has been detected.

The counter used to count these 463 times (:
Set 463 in NT1115. Since it is possible to analyze the frequency once every two periods, these 463 times are a total of 463 x - x 2 = 0, 18 of 5 seconds.
50) corresponds to detecting 12.

In step 5290, it is determined whether a 300 b/s byte clock has occurred. Specifically, it is determined whether a clock is generated on the signal line 28a.

When a byte clock of 300 b/s is generated, that is, when a clock is generated on the signal line 28a, step 53
Proceed to step 32. On the other hand, when a 300 b/s byte clock is not generated, that is, when no clock is generated on the signal line 28a, the process advances to step 5292.

In step 5292, it is determined whether FLGIDT is "0", that is, whether a continuous 2-byte flag pattern (7EH) has been detected. When FLGIDT is "Oj", that is, when a 2-byte consecutive flag pattern (7EH) is not detected, the process advances to step 5294. Also, when FLGIDT is "1", that is, when a 2-byte consecutive flag pattern (7EH) is not detected, the process proceeds to step 5294. Flag pattern (7
E) When I) is detected, the process advances to step 5306 and no analysis of the tonal signal is performed.

In step 5294, SED (Signal
It is determined whether or not EnergyDetect) is "1", that is, whether the signal level of the signal line 36a is "1". When this SED is "1", that is, when the signal line 36a is at the signal level "1", the process advances to step S2' 96 to analyze the tonal signal.

On the other hand, when SED is rOJ, i.e. signal line 36
When a is the signal level "0", the process advances to step 5306 and no tonal signal analysis is performed.

Steps 5292 and 5294 above are features specific to tree implementations.

In step 5296, it is determined whether the analysis of one period of the tonal signal has been completed, that is, whether a pulse has occurred on the signal line 34a.

When the analysis of one period of the tonal signal is completed, that is,
When a pulse on signal line 34 occurs, the process proceeds to step 5298. On the other hand, if the analysis of one period of the tonal signal has not been completed, that is, if no pulse is generated on the signal line 34a, the process advances to step 5306.

In step 5298, tonal data (ie, the signal on signal line 34b) is input.

In step 5300, it is determined whether the one-cycle signal just received is 1850H2. If the currently received one-cycle signal is 1850 Hz, the process advances to step 5302. The signal of one period just received is 1850
If it is not Hz, the process advances to step 5306.

In step 5302, it is determined whether the value of the counter CNT185 is negative, that is, whether the signal of 1850)1z has been detected for a total of 0.5 seconds or more. When the value of counter CNT185 is negative, that is, 185
0) When the 1z signal is detected for a total of 0.5 seconds or more, the process advances to step 5306. Also, the counter (:NT
When the value of 185 is positive or flat, i.e. 1850
If no Hz signal has been detected for a total of 0.5 seconds or more, the process advances to step 5304.

In step 5304, the value of counter CNT185 is decremented by one.

In step 5306, it is determined whether or not consecutive 5ED=O of 200 m5 or more have been detected. Here, even if there is background noise, the randomness of the signal is checked to determine if the signal is disconnected.

If a continuous signal disconnection of 200 m5 or more is detected, the process advances to step 5308. Further, if a continuous signal disconnection of 200 m5 or more is not detected, the process advances to step 5326.

In step 5308, it is determined whether the value of the counter CNT185 is negative, that is, whether the signal of 1850)1z has been detected for a total of 0.5 seconds or more. When the value of counter CNT185 is negative, that is, 1115
When a 0 Hz signal is detected for a total of 0.5 seconds or more, the process proceeds to step S:]IO. When the value of the counter (:NT185 is positive or ;, that is, when the 1850H2 signal is not detected for a total of 0.5 seconds or more, step 5320
Proceed to.

In step 5310, a signal disconnection is detected, and
Since the total number of signals of 1850112 has been detected for more than 0.5 seconds, GI2CNT is incremented by 1.

In step 5312, it is determined whether FLGIDT is "o". Here, FLGIDT is “o
”, the process advances to step 5314. On the other hand, FLG
If IDT is not "0", the process advances to step s3°18.

In step 5314, it is determined whether the counter GI2DET is less than 2, that is, whether the GI2 signal has been received less than twice. If the counter GI2DET is less than 2, that is, if the GI2 signal has been received less than twice, the process proceeds to step 5320.

Further, if the counter GT2DET is 2 or more, that is, if the GI2 signal is received twice or more, step 5
Proceed to 316.

In step 5316, it is determined that the other device is 62, and the process proceeds to G2 mode transmission.

In step 5318, it is determined whether the counter GI2DET is less than 3, that is, whether the GI2 signal has been received less than three times. If the counter GI2DET is less than 3, that is, if the GI2 signal has been received less than three times, the process proceeds to step 5320. On the other hand, if the counter GI2DET is 3 or more, that is, GI2
If the signal has been received three times, proceed to step 5316.

Steps 5300 to 5318 are functions unique to this embodiment.

Step 5320 is FLGIDTl: r
Set OJ.

Step 5322t: Oiteha, F, LGDET&:
r Set OJ.

In step 5324, counter CNT185 is set to r4B3J.

In step 5326, it is determined whether timer T1 has timed out. When the timer Tl times out, the process advances to step 5328. Also, when timer T1 has not timed out,
Proceed to step 5290.

In step 5328, the telephone line is connected to the telephone side. Specifically, the signal level "0" is applied to the signal line 38a.
Outputs the signal.

Step 5330 represents an error.

Steps 5332 to 5362 are shown in FIG.
3) corresponds to steps 5162 to 5192 shown in (4).

The determinations in step 5356 and step 5358 described above are functions unique to this embodiment.

In step 5364, it is determined whether the frame just received is the last frame.

If the received frame is the last frame,
Proceed to step 5366. Further, if the currently received frame is not the last frame, the process advances to step 5370.

Step 5366 is step 5 shown in FIG. 5(5).
Detection of carrier disconnection as described in steps 212 to 5240 is performed. This is an effect unique to this embodiment.

Step 5368 indicates that the reception of the 300b/S binary signal is completed and the process proceeds to the next operation based on the received signal.

In step 5370, FLG[lET r□,
Set.

In step 5372, (:NTBYT is set to "0")
Set.

In FIG. 8 described above, when a 300 b/s byte clock is generated (determined in step 5290),
Heading to the analysis of 300b/s. And 300b/s
In the analysis, if it is not determined that a binary signal has been received, the process proceeds to step 5292.

Furthermore, when the analysis of one cycle of the tonal signal is completed (determined in step 5296), the process proceeds to the analysis of the tonal signal. Then, in the analysis of the tonal signal, if it is not determined that a tonal signal has been received, the process advances to step 5290.

In this way, when it is necessary to receive tonal and binary signals simultaneously, it is possible to always receive tonal and binary signals without overlooking all the received signals. This is a feature unique to this embodiment.

Note that in the embodiments described so far, G2. Although the facsimile device having the G3 function has been described, it goes without saying that the present invention can be applied to other communication devices.

(Hereinafter, blank space) [Effects of the Invention] As described above, according to the present invention, since the configuration is such that tonal signals and binary signals can be identified without error, it is possible to perform appropriate communication control between communication devices. It becomes possible.

Furthermore, according to the present invention, even if an error occurs during reception of the V21 signal, for example, and it becomes impossible to receive the binary signal currently being received, this is mistakenly recognized as detection of a tonal signal. Things will go away.

Furthermore, according to the seventh embodiment of the present invention, it is possible to interrupt tonal signal reception control during a no-signal period, so that noise or the like during the no-signal period can be interrupted.

There is no possibility of misidentifying it as tonal signal detection. 17' /-′ one'

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a facsimile device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a facsimile device to which the present invention is applied, FIG. 3 is a diagram for explaining a tonal counter, and FIG. The figure is a flowchart showing the control procedure to be executed by the control circuit 38 on the image receiving side. 5(1) to 5(5) are flowcharts showing detailed IJIQ1 procedures to be executed by the control circuit 38 as the image ff receiving side, and FIG. 6 shows the operation when storing received binary data. figure. FIG. 7 is a flowchart showing the control procedure to be executed by the 1v control circuit 38 as the image transmitting side, and FIGS. It is a flow chart showing a control procedure. 2...NC:Ll. 4...Pa1 [Shikiki. 6...Hybrid circuit, 8...Reading circuit, LO...Encoding circuit. +2・-・V27 te r Arui is V29 strange A'l
A, 14... Parallel/serial conversion circuit, 16...
・V21 modulator. 17...CI2 signal sending i1j circuit circuit 8...Addition circuit. 20 -- V27 ter or V29 demodulator, 2
2... Reconstruction circuit, 24... Recording circuit, 26... V21 demodulator, 28... Real/'parallel conversion circuit. 30...PI width circuit, 32...21t1 conversion circuit. 34...-1-null counter circuit, 36... Signal black detection circuit, 38... Control circuit. Figure 3 Figure 6

Claims (1)

[Scope of Claims] 1) A data receiving device having a function of receiving binary signals and tonal signals, comprising a control means for interrupting reception of tonal signals and receiving binary signals under predetermined conditions. A data receiving device characterized by: 2) When the control means detects at least n predetermined flag patterns, the control means interrupts the reception of the tonal signal and only receives the binary signal. data receiving device. 3) The data receiving device according to claim 1, wherein the control means interrupts reception of tonal signals and only receives binary signals when detecting a signal-off state. .