JPS62293476A - Picture processor - Google Patents

Abstract

PURPOSE:To attain more than two processing by individually switching addresses of two systems including a picture inputting and outputting address and a picture processing address every picture memory. CONSTITUTION:An address selector 9a corresponding to the picture memory 1a is set to an inputting and outputting address selection mode by a selection signal (S) from an MPU6 and an address selector 9b corresponding to the picture memory 1b is set to an address selection mode for the MPU by a selection signal (Sb) from the MPU6, and then, the picture data of an object photographed by a television camera 2 is stored in the picture memory 1a through a data bus DB1 and the picture data which is already stored is read through a processing data bus DB2 from the picture memory 1b and transmitted to a microprocessor 6.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present elJ1 relates to an image processing device that simultaneously performs two or more processes.

(Prior Art) Recently, a method for recognizing the shape and movement of an object from an image taken by a television camera has been known as one of the methods for recognizing objects, and an image processing device for this purpose is being considered (for example, (Japanese Patent Publication No. 61-26186-3). No. 21m is a block diagram showing an example of a conventionally known image processing device of this type, and Ia, lb, . performs A/D conversion on the image received from the television camera 2, D/A converts the image data read out from the image memory 1a, lb,...In, and outputs it as an image signal. An image input/output unit outputs a synchronization signal; 4 is a monitor that directly displays the object photographed by the television camera 2 or reproduces an image of the object stored in the image memory; 5 is an image input unit 3 An input/output address generation unit generates an input/output image memory address (hereinafter referred to as "input/output address") based on a television synchronization signal; 6 is a microprocessor (hereinafter referred to as "r") that performs image processing;
7 is an MPU address generation unit that generates an image memory address (hereinafter referred to as rMPU address) used in image processing, and 8 is an input/output address generation unit based on a selection signal t)S from the MPU 6. This is an address selector that switches between the image memory address from 5 and the image memory address from MPU address generation section 7.

In the image processing device of No. 112, there are a data bus DB for image input/output and a data bus DB2 for image processing as data buses, and the address bus AB is connected to the address selector 8, and the address bus AB is connected to the address selector 8, and the input address and MPU address are switched and sent to each image memory.

By the way, in image processing devices for research and development, it is often necessary to continuously display events that change one after another, or to perform two or more processes at the same time to increase speed.
. In the PLJ image processing device as described above, there is only one system for the image memory address, input/output movement, and MPU river, so for example, the image processing memory has M in la, lb, -1n.
Since the PU address is sent, the image data read out from the image memory based on this MPU address is also sent to the image output section 3, causing the screen on the monitor 4 to flow. Also, during this image processing, it is of course impossible to store the image data of the object photographed by the television camera 2 in the image memory. Conversely, during image input, the manual address is sent to the image memory, and the MPU 6 cannot process the image during this time.

(Purpose and Structure of Issue 151) The present invention has been made in view of the points listed in L. At least two systems of addresses including an image input/output address and an image processing address are independently switched for each image memory. It was configured as follows.

(Example) The present invention will be explained below based on the drawings.

FIG. 1 shows an embodiment of an image processing apparatus according to the present invention, and the same reference numerals in FIG. 1 as in FIG. 2 indicate the same components.

In this embodiment, an address bus AB for transmitting input/output addresses and buses A) to AB2 for transmitting MPU addresses are provided separately, and an input/output address and an MPU address are provided for each image memory. Address selector 9a for switching.

9b, . . . 9n are provided. These address selectors 9a, 9b, . . . 9n receive selection signals from the MPU! ;
Sa, Sb, . . . -S n can be independently switched.

Let us now consider a case where image data of an object photographed by the television camera 2 is not stored in the image memories la, lb, .

For example, the address selector 9 corresponding to the image memory 1a
a to the input/output address selection mode by the selection signal Sa from the MPU 6, and set the address selector 9b corresponding to the image memory 1b to the MPU address selection mode by the selection signal sb from the MPU 6. The image data of the object photographed by the television camera 2 is stored through the image input/output data bus DB, and the already stored image data is read out from the image memory lb through the image processing data bus DB2 and sent to the microprocessor. It is sent to processor 6.

Similarly, if the address selector 9a is set to the input/output address selection mode by the selection signal Sa, the image memory l
Either the image data stored in a is read out through the image input/output data bus DB, sent to the image input/output unit 3, and reproduced on the monitor 4 (without the monitor screen flowing), or this 11f current image After monitoring the image data, the MPU 6 can process the image data read out from the image memory 2b.

In this embodiment, the system is not limited to the two systems described above, but a certain bias value is added to the image input/output address of one image memory to create another image processing address, and the MPU address of that image memory is If a selector that adds another constant bias value to the address and uses it as another MPU address is provided as the address of another image memory, the simultaneous processing of four systems can be repeated. In this case, since a constant bias can be provided between the read address and the write address in image processing, address setting for one image processing becomes easy.

Also, when outputting an image, set a bias value of 4 to the image output address.
You can scroll or move by changing the number.

(Effects of the Invention) As explained in Section 1 below, in the present invention, at least two systems of addresses including image input/output addresses and image processing addresses are independently switched for each image memory. Once configured, two or more processes can be performed at the same time, such as capturing image data and displaying the contents of the image memory while performing image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an image processing apparatus according to the present invention, and FIG. 2 is a block diagram of an example of a conventional image processing apparatus. la, lb, = In... Image memory, 2... Television camera, 3... Image input/output unit, 4... Monitor, 5
. . . Input/output address generation unit, 6 . . Microprocessor, 7 . . MPU address generation unit, 8.9a. 9b...9n...Address selector patent applicant [
Isan Jidosha Co., Ltd. Agent Patent Attorney Hiroshi Suzuki Figure 1 Figure 2

Claims (1)

[Scope of Claims] A plurality of image memories that store image data, a first address generation section that generates an address for inputting the image data to the image memories, and a first address generator that generates an address for inputting the image data to the image memories; a second address generation unit that generates an image processing address to be read for image processing; and an address selector that independently switches between an input/output address and an image processing address for each image memory and sends it to the image memory. An image processing device comprising: an image processing unit that performs image processing using image data read from an image memory based on an image processing address.