JPS6230701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor device in which a plurality of semiconductor element chips are attached to a single substrate and these semiconductor element chips are connected in parallel to increase the capacity.

FIG. 1 is a perspective view showing a conventional example of this type of semiconductor device, and FIG. 2 is a circuit connection diagram thereof. In the figure, 1a and 1b are transistor chips, 2 is a common collector terminal connected to the collectors of both transistor chips 1a and 1b, 3 is a similar common emitter terminal, 4 is a common base terminal, and 5 is a common terminal of both transistors 1a and 1b. Connecting conductor between emitters,
6 is an insulating plate, 7 is a substrate, and 8 is a parasitic inductance possessed by the emitter-to-emitter connection conductor 5.

In such a conventional device, collector common terminal 2
Normally, a DC power supply is connected in series with a load resistor between the terminal and the emitter common terminal 3, and a base signal is input to the base common terminal 4 to operate the switch. explain.

When a positive base signal is supplied to the base common terminal 4 of the npn transistors connected in parallel as shown in the figure to turn both transistors 1a and 1b on, an imbalance occurs in the rise of the collector currents of both transistors 1a and 1b. arise. FIG. 3 is a waveform diagram showing this imbalance. In the figure, i _ca and i _cb are transistors 1a and 1b, respectively.
is the collector current of . That is, when transistors 1a and 1b are turned on, a potential difference _VLS occurs between point A and point B. The potential difference V _LS is the rise of the collector current of the transistor 1a as di _ca /dt,
If the parasitic inductance 8 is L _s , then V _LS =L _s × di _ca /dt, and the potential at point A is higher than point B by V _LS . Therefore, although the base potentials of transistors 1a and 1b are the same, more base current flows into transistor 1b than transistor 1a, and the collector current i _cb becomes smaller than the collector current i
becomes larger than _ca. Therefore, the rise of the collector current i _ca is delayed.

In this way, with the conventional device, it is not possible to obtain the required output current (corresponding to the number of parallel transistors) in response to the base input.
It had the disadvantage that a large responsibility was placed only on b, and it was easy to destroy.

This invention has been made in view of the above points, and includes a conductor wiring to which the main electrode of each semiconductor element chip is connected, a main electrode connection wiring part for connecting the main electrode to the conductor wiring, and the wiring. and a folded wiring section that is provided close to and parallel to the common terminal, one end of which is connected to the end of the wiring section opposite to the common terminal installation side, and the other end of which is connected to the common terminal. By doing so, it is possible to cancel out the parasitic inductance of the main electrode connection wiring section, prevent differences in the rise of the main currents of semiconductor elements connected in parallel, and furthermore, it is possible to flow evenly balanced currents from the point of rise. The purpose is to provide a semiconductor device that can perform

FIG. 4 is a perspective view showing a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a circuit connection diagram thereof.
In the figure, the same parts as in the conventional example are indicated by the same reference numerals, and the explanation thereof will be omitted. 9 is provided close to and parallel to the emitter-to-emitter connecting conductor 5, one end is connected to the end of the emitter-to-emitter connecting conductor 5 on the opposite side to the side where the emitter common terminal 3 is installed, and the other end is connected to the common terminal. The folded conductor 8a connected to the folded conductor 3 is the parasitic inductance of the folded conductor 9.

In the device of this embodiment having such a configuration, the mutual inductance between the emitter-to-emitter connecting conductor 5 and the folded conductor 9 is M, and the current flowing through the folded conductor 9 is i.
_c , and let parasitic inductance 8a be Ls', V _M = M × di _c / dt (here, M = k√ _S・_S ', a is the current flowing in L _S '/current flowing in L _S , and k is (The coupling coefficient is -1k+1.) An electromotive force V _M is generated, and since this electromotive force V _M is in the opposite direction to the potential difference V _LS generated in the emitter-to-emitter connecting conductor 5, the potential difference V _LS can be expressed as It works to cancel it out.
That is, _VLS - _VM , and the potential difference between points A and B decreases. Therefore, it is possible to prevent a difference in the rise of the main currents of both transistors 1a and 1b.
Furthermore, by arranging the folded conductor 9 with an appropriate spacing from the emitter-to-emitter connecting conductor 5 and thereby appropriately setting the mutual inductance M, the potentials between A and B become equal, and the base current flows equally into transistors 1a and 1b, and the collector current flows equally into both transistors 1a and 1b from the time of rising.
The effect of parallel connection can be fully achieved.

6 and 7 are circuit connection diagrams respectively showing a conventional example and another embodiment of the present invention when three or more transistors 1a, 1b, . . . 1n are connected in parallel; As in the case of , the effect of the parasitic inductance of the emitter-to-emitter connection conductor 5 is canceled by the folded conductor 9, and the effect of the parallel connection is fully exhibited.

Although the above embodiments have been described using transistors, the present invention can also be applied to cases where other semiconductor switching elements are used.
It has a similar effect.

As detailed above, according to the semiconductor device of the present invention, in a device in which a plurality of semiconductor element chips are arranged on the same substrate and connected in parallel, the conductor wiring to which the main electrode of each semiconductor chip is connected is , a main electrode connection wiring part for connecting the main electrode thereto, and a main electrode connecting wiring part provided close to and parallel to the wiring part, one end of which is located at the end of the wiring part on the opposite side from the common terminal installation side. Since the wiring is connected to the folded wiring section and the other end is connected to the common terminal, the negative effect of the parasitic inductance of the connecting conductor is eliminated, and there is no difference in the rise of the main current of the plurality of semiconductor elements. can be prevented from occurring, and furthermore,
This has the effect of allowing current to flow equally through each semiconductor element from the time the main current rises, thereby fully achieving the effect of parallel connection.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an example of a conventional semiconductor device, FIG. 2 is a circuit connection diagram thereof, FIG. 3 is a waveform diagram showing current imbalance in the conventional example, and FIG. 4 is an embodiment of the present invention. A perspective view showing a semiconductor device according to an example, FIG. 5 is a circuit connection diagram thereof, FIG. 6 is a circuit connection diagram showing another example of a conventional semiconductor device, and FIG. FIG. 7 is a circuit connection diagram showing a semiconductor device according to another embodiment of the invention. In the figure, 1a, 1b,...1n are transistors (semiconductor elements), 3 is an emitter common terminal,
5 is an emitter-to-emitter connection conductor (conductor wiring), 6 is an insulating plate, 7 is a substrate, 8 and 8a are parasitic inductances,
9 is a folded conductor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A plurality of semiconductor element chips are mounted on a single substrate, each corresponding electrode of these semiconductor element chips is sequentially connected to each conductor wiring formed on the substrate, and one end of the corresponding electrode is connected to each conductor wiring formed on the substrate. In a semiconductor device in which the semiconductor element chips are connected in parallel with a common terminal of the corresponding electrodes provided on the side thereof, the conductor wiring to which the main electrode constituting the main current path of each of the semiconductor element chips is connected is a main electrode connection wiring section for connecting the main electrode thereto; and a main electrode connection wiring section provided close to and parallel to the wiring section, one end of which is connected to the end of the wiring section on the opposite side from the common terminal installation side. , and a folded wiring portion whose other end is connected to the common terminal.