JPS6231100A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To easily perform a test without providing a special means for testing a memory circuit even when it is mixed with a logic circuit by having a latch circuit as an information reading output part and providing a reading circuit in which a mode is changed over by the externally designated mode change over information. CONSTITUTION:The writing information inputted to writing information input terminal groups 12 is fed to a memory cell 20 through a writing information buffer circuit 22. The reading information read from the memory cell 20 is inputted to a reading circuit 23. In the reading circuit 23, by the control information inputted to reading circuit control input terminal groups 14, whether the reading information read from the memory cell 20 is outputted to reading information output terminal groups 13 as it is or the reading information is latched and outputted to the reading information output terminal groups 13 is controlled. The information latched in the reading circuit 23 by a shift operation of the control information of the reading circuit control input terminal groups 14 is outputted to a reading information shift output terminal 15.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory integrated circuit (hereinafter referred to as "memory IC") in which a logic circuit and a memory circuit coexist.

(Prior art) Memory ICs can be configured as separate and independent memory circuits, for example, in units of memory cards, and consideration has been given to making testing of the memory circuit part easy. .

In recent years, with the remarkable progress in IC technology, not only logic IC elements but also p-memory IC elements have become faster and larger in capacity.

Memo: Logic IJIO is a means of increasing the speed and capacity of IJIO elements and achieving higher performance of logic devices.
A configuration in which a C element and a memory IJIO element are mixed is becoming commonly adopted.

(Problem to be solved by the invention) Therefore, in order to test the memory circuit section in the above circuit, it is necessary to provide dedicated input/output terminals or add a circuit used only for memory testing. However, there was a problem with the circuit configuration.

An object of the present invention is to solve the above-mentioned drawbacks, and to provide a memory integrated circuit that can be easily tested without providing special means for testing memory circuits even when mixed with logic circuits. There is a particular thing.

(Means for Solving the Problems) To achieve the above object, a memory integrated circuit according to the present invention has integrated circuit memory cells arranged in rows and columns,
In a random access integrated circuit, information is read from a specific memory cell corresponding to address information given from the outside, or write information given from the outside is written to this memory cell by inputting a write pulse given from the outside. As a readout output section, a readout circuit consisting of a latch circuit whose mode is switched according to mode switching information specified from the outside is provided, and is configured so that either readout information through mode or latch mode with shift function can be selected.

According to the above configuration, the readout circuit can output normal readout information, and the readout information can be taken out as shift column information by switching, so that testing becomes easy and the object of the present invention is completely achieved.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory integrated circuit according to the present invention.

The write information input to the write information input terminal group 12 is sent to the memory cell 20 through the write information buffer circuit 22.

Address information and memory control information are input to address information and memory control information input terminal group 11 and sent to memory cell 20 through n1 address buffer circuit and memory control circuit 21. A write operation or a read operation designated by the memory control circuit is performed on a specific memory cell selected by the address buffer circuit output.

The read information read from the memory cell 20 is sent to the read circuit 23.
Enter.

The readout circuit 23 outputs the readout information read from the memory cell 20 as it is to the readout information output terminal group 13 according to the control information input to the readout circuit control input terminal group 14, or latches the readout information and outputs the readout information to the readout information output terminal. Controls whether to output to group 13.

Furthermore, the information latched in the readout circuit 23 is outputted to the readout information shift output terminal 15 according to the control information shift operation designation of the readout circuit control input terminal group 14 .

FIG. 2 is a detailed diagram of the readout circuit 23 shown in the block diagram of FIG. 1.

In the read information through function mode operation, the read information read from the memory cell is input to the read information input 16, selected by the read shift information switching circuit 41, and transferred to the master latch circuit 42.
Enter.

Since the master latch circuit 42 is set to the through function mode by the designation of the clock input terminal 31 in the readout circuit control input terminal group, the readout information is in the through function mode. It is output to the read information output terminal.

In the latch mode operation with read information shift function, the normal read information output is the same as in the through function mode operation described above except that the read information is latched by the master latch circuit according to the designation of the clock input terminal 31.

In the shift function operation, the shift mode designation input terminal 32 in the readout circuit control input terminal group 14 is set to the shift mode, and the readout shift information switching circuit 41 is set to the shift information input terminal 3.
3 to the shift information input and output of each readout circuit 4o are set in a connected circuit system to form a shift column.

The read information latched by the slave latch circuit 43 is outputted to the read information shift output terminal 15 through the shift column.

(Effects of the Invention) The present invention has been described in detail above.The readout information output section is provided with a readout circuit having a mode-switchable latch circuit, and by setting the latch circuit to the readout information through mode, the present invention has the same function as the conventional one. By setting the latch circuit to a latch mode with a shift function, it operates with the same function as the conventional one, and the read information can be taken out as information of all shift columns. Therefore, it becomes easy to test a circuit in which a logic circuit and a memory circuit are mixed, and it has the effect of being an effective means for debugging and fault detection when incorporated into a device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory integrated circuit according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a readout circuit. 11... Address information and memory control information input terminal group 12... Write ↑ NN large input terminal group 3... Readout information output terminal group] 4... Readout circuit control input terminal group 15... Research Output 1 blue report shift output terminal] 6...d Output information 20...Memory cell 21.
... Address buffer circuit and memory control circuit 22 ... Write f# signal buffer circuit 23 ... Read circuit 31 ... Clock input terminal 3
2...Shift mode designation input terminal 33...Shift information input terminal 40...1 bit read circuit 41...Read shift information switching circuit 42...Master latch circuit 43...Slave latch circuit

Claims (1)

[Claims] It has integrated circuit memory cells arranged in rows and columns, and information can be read from a specific memory cell corresponding to address information given from the outside, or by inputting a write pulse given from the outside to this memory cell. In a random access memory integrated circuit that writes write information given by a latch circuit as an information read output section,
1. A memory integrated circuit comprising a readout circuit whose mode can be switched in accordance with externally designated mode switching information, and configured to select either a readout information through mode or a latch mode with shift function.