JPS6231258A - Two-dimensional encoding device for image signals - Google Patents

Abstract

PURPOSE:To execute an encoding action without being late for the input of a picture signal by generating simultaneously the encoding code of respective modes and selecting and outputting this in accordance with the priority sequence. CONSTITUTION:By the output 228 of a run length counter 203, the value, color, etc., of the run length are given to a ROM table C206, the equivalent code and the code length are outputted from a ROM206. In the pre-stage where by ROM tables 204, 205 and 206, respective codes of a P mode, a V mode and an H mode are determined to be the code to be generated finally, when two or above are outputted from the ROM table simultaneously, by the sequence of the P mode > the V mode > the H mode, the code of the mode obtaining the priority is determined as the code to be generated finally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a two-dimensional encoding device for image signals used in facsimiles and image electronic file registers.

[Prior art]

In conventional facsimile T image transmission devices and recent image file devices using optical disks, magnetic disks, etc., one image value code is encoded and handled, reducing the amount of data and speeding up transmission or storage operations. We are trying to improve efficiency.

For example, in the field of facsimile, the modified Huffman (MH) method is generally used for one-dimensional encoding, the modified read (MR) method is used for two-dimensional encoding, and the modified modified read (MMR) method is used for high-gloss two-dimensional encoding. ing.

Regarding the mutual relationship between these MH method, MH method, and MMR method, the MMR method includes methods that are very similar to the MH method, and the MMR method is a partially modified version of the MH method.

Furthermore, the image to be encoded and the rules for the encoding method are, in a nutshell, based on T4 and T6 recommended by the CCITT (Consultative Committee on International Telegraph and Telephone).

Furthermore, the encoding method described in E was introduced in March 1986 regarding the MMR method.
The MH method is announced as a high-efficiency two-dimensional encoding method in the recommended communication method for facsimile group 4 type equipment (Postal Service-Kuhi) on page 52 or less of the official gazette (extra issue No. 29) dated May 22nd. Both the original encoding method and the MR method are two-dimensional encoding methods as per Ministry of Posts and Telecommunications Notification No. 1013 of 1982.
It is announced in the number.

Among the aforementioned encoding methods, the one-dimensional encoding of the MR method and MMR method determines the correlation between the image signal of the line to be encoded and the image signal of the previous line, and generates an encoding code of a mode according to this correlation. This is a configuration that generates. Therefore, after determining the correlation, the encoding operation in the corresponding mode is performed, but for example, it is difficult to encode an image signal obtained by photoelectrically reading an original image without delay.

〔the purpose〕

The present invention has been made in view of the above points, and the above-mentioned M
The purpose is to make it possible to perform one-dimensional encoding of R and MMR images at high speed without requiring the human power of the image to be encoded. L stage that serially captures the image signal of the reference line in synchronization with the serial input of the signal, and the number of images (images) between the conversion points of the image signal of the encoding line are counted and the encoded code is generated based on the total a value. a first generating means for monitoring the correlation between the image signal of the encoded line and the image signal of the reference line, and generating an encoded code based on the correlation; Encoded codes can be generated simultaneously from stages f
It is an object of the present invention to provide a two-dimensional encoding device for an image signal, which has a selection means for selecting an encoding code to be output according to a predetermined priority order when the encoding code is negative.

〔Example〕

Examples of the configuration of an encoding circuit to which the present invention is applied are shown in Figures 1 and 2.
The operation of the embodiment shown in the circuit block diagram in the figure will be explained using FIGS. 1, 2, 3 to 5, etc.

In FIG. 1, the signal indicated by 121 is an image signal to be encoded supplied from an external device such as an image scanner, an image file, or a computer.
For example, it is given as serial data of a binary signal of "l OIT = white, "1" = black pixel). Also, the signal indicated by 134 is a clock supplied from an external device in synchronization with the input of the image signal 121. There is one clock per pixel.The next signal shown at 136 is a synchronization signal.
Several types of synchronization signals indicating horizontal sections, vertical sections, etc. of the image signal 121 are shown.

That is, in this embodiment, the image signal 121 to be encoded is provided as a scanning image signal that is a serial image signal for each main scan, similar to a signal provided to a laser printer or the like.

Next, 101 is a forced change so that the next pixel (blind virtual pixel) after the last pixel of the real image on the coding red line (one line in the main scanning direction of the image to be encoded) is always the change point. This is a circuit that generates points, and is called a "virtual change point generation circuit A." However, the above-mentioned "virtual change point generation circuit A" has a structure that does not give any change to the real image on the coding line.

102 is a line buffer memory A, and lO3 is a line buffer memory B, each of which is a RAM (random access memory) that can write or read independently. It has a capacity (number of main scanning pixels) that can store a value image.

Further, the line buffer memory Al02 and the line buffer Φ memory B103 are controlled so that when one is performing a write operation, the other is performing a read operation. In other words, these two line buffer φ memories constitute a set of double-line buffer memories.

111 is a memory address counter that counts the clock 134 corresponding to the number of pixels of the coding line. Commonly provided to both AlO2 and line buffer memory B102.

The memory address number counter 111 returns to the initial value for each coding line and repeats the counting operation. Therefore, the binary image of each line written to the line buffer memory is the image signal 121 of the newly input line.
is read out for each pixel in association with the pixel position.

104 is a selector, and line buffer memory A
Of lO2 or line buffer memory B103,
This is a circuit that performs a selection operation using a select signal 901 in order to execute a read operation and obtain read data from one of the two.

The data selectively obtained by the selector 104 is given to the next stage as a reference line 125, that is, as reference data (image) of the coding line.

105 is a circuit that forcibly creates a change point so that the last pixel of the real image on the reference line and the next pixel (virtual pixel) always become the change point, and is called "virtual change point generation circuit B".
”.

However, the virtual change point generation circuit Bl 05 is the reference Φ
The structure is such that no change is made to the actual image on the line.

Reference numeral 106 denotes a circuit that detects a pixel serving as a changing point on the real image and virtual pixel on the reference line, and is referred to as a "changing point detection circuit A."

Further, 107 is a circuit for detecting changing points on the real image and virtual pixels on the coding line, ``changing point detection circuit B''.
It is called.

108 is A register, 109 is B register, 110 is C
The signals indicated at 126 are signals representing the real image and virtual pixels on the reference line, and the signals indicated at 127 represent the real image on the Farenne φ line. and a change point signal on the virtual pixel. The signal indicated at 128 is the coding signal.
These are the real image on the line and the change point signal on the virtual pixel.

Reference numeral 112 denotes a timing circuit which receives a clock 134 and a synchronization signal 136 as input, and forms various timing signals 137 for timing the operation of each circuit block based on these signals.

The operation of the circuit block of FIG. 1 described above will be explained using an example in which an actual image (an image to be encoded) as shown in FIG. 4 is given and is encoded by the MMR method.

First, in order to simplify the explanation, the image shown in FIG. ) to create an extremely simple image that makes up one page.

To actually encode the first line shown at 402 in FIG. 4, as shown in FIG. 5, the virtual line shown at 401 in FIG. do.

When encoding the second line 403 in FIG. 4, the first line 402 in FIG. 4 is used as a reference line and the second line 403 is used as a coding line, as shown in FIG. 6.

Below, it is assumed that one page consists of main scanning of 3 or more lines,
Even if the third line, fourth line, etc. continue, as described above, if the relationship between the reference line and the coding line is sequentially lowered, encoding will continue regardless of the number of sub-scanning lines. can.

FIG. 3 is a timing chart when the image illustrated in FIG. 4 is applied to the circuit block illustrated in FIG. 1.

In FIG. 3, reference numeral 1-38-1 is a vertical synchronizing signal indicating an image section in the sub-scanning direction, that is, an input period of one page of images. 136-2 is a horizontal periodic signal indicating an image section in the main scanning direction, that is, an input period of an l-line image. 134 is an image clock, 121 is a signal waveform representation of the image to be encoded illustrated in FIG. 4, and black pixel = "lH = l
j H+1, white pixel=゛0"=°"L11. That is, among the images shown in the third figure, the image in section T1 is the actual image in the first line 402 shown in the fourth figure to be encoded, and the image in section T2 is the real image in the second line 403 shown in the fourth figure to be encoded. This is a real image.

Furthermore, in an image printed on actual paper, the virtual line 401 shown in the fourth figure corresponds to the upper part of the paper, a blank space, or the outside of the paper, and in the MMR method, is defined as a blank line (all pixels in one line are white pixels). Therefore, the virtual line 401 shown in the fourth figure does not appear on the image signal 121 shown in the third figure.

FIG. 5 is a timing chart showing the encoding operation of the first line 402, and shows the relationship between the virtual line 401 serving as the reference φ line and the first line 402 serving as the coding.

First, when the image of the first line 402 shown in FIG. 5 is given to the virtual change point generation circuit A101, a virtual change point (virtual pixel) 302 is added as shown at 122 (coding line) in FIG. It becomes an image. That is, in the interval T1, the actual image remains unchanged, but as shown in the figure, the last pixel 301 of the first line and the next pixel 302 have contradictory colors (:
white → black), and virtual change point (virtual pixel) 30
Several virtual pixels following 2 are held as pixels of the same color as the virtual change point (virtual pixel) 302 so that they do not become change points for reasons described later.

Now, the coding fist line signal 122 in FIG.
As shown in FIG. 1, is input to the change point detection circuit B107 as an image signal to be encoded, and is also given as write data to the line buffer memory AlO2 and line buffer memory B103.

On the other hand, the address counter ill counts the image clock 134 only in interval T1 in FIG. 3, outputs a count value as shown at 135 in FIG. AlO2
and the line buffer memory B103.

Furthermore, although not shown in the figure, assuming that the line buffer memory Al 02 is controlled to the write mode and the line buffer memory B 103 is controlled to the read mode, the data of the coding line 122 is controlled to the line buffer memory. They are sequentially written to the addresses indicated by memory address 135 in AlO2. Also, at this time, the line buffer reference memory B103 is in the read mode as described above, so if all "°0" are written in the initial state, the data will be read from the address specified by the memory address 135. 0°' is sequentially read out to become a read signal B shown at 124 in FIG.

Reference numeral 125 in FIG. 3 indicates the data signal waveform of the reference line, which is "O" during one section Tl.
It was obtained on the circuit as a completely white reference line.

The coding line 122 is also applied to the change point detection circuit B107 as described above. The detection circuit B107 detects a change point (pixel) in the given data input, outputs the change point pixel as "1 pixel", and outputs all pixels that are not a change point as "0". 128 in FIG. 1 is the output.

Virtual change point generation circuit B105 and change point detection circuit A10
6, as its name suggests, is the coding line 1 mentioned above.
Circuits 101 and 10 with the same name operating on 22
7 is performed on the reference line 125 read from the linebacker memory.

Eventually, the signal on the reference line 125 is converted by the virtual change point generating circuit B105 into a signal in which a virtual pixel of a color different from the last pixel is added next to the last pixel, as shown at 126 in FIG.

The signal 128 generated from the change point detection circuit B107 is sequentially shifted into the A register 108 by the clock 134. Symbols A1 to A4 of the A register 108 each indicate the parallel 4-bit output of the corresponding jitter, which is always output. The output signal waveforms of the A register 108 are shown at 129-1 to 129-4 in FIG.

Therefore, the pixel of interest on the coding line is A register 1.
If it is shifted to output A4 of 08, output 1 indicates whether there is a change point in the data for 3 pixels following that pixel of interest.
The coffin can be determined by 29.

Similarly, 130-1 to 130-4 in Figure 3 and 1 in Figure 3
31-1-131-4 shows the output signal waveforms of the B register 109 and the C register 110, that is, the B register 10
The change point signal and color signal of the pixel of the reference line corresponding to each pixel position stored in the A register 108 are stored in the 9 and C registers 110. Therefore, if the output A4 of the A register 108 is the pixel of interest on the coding line, the B register 109 and the C register 1
10, it is possible to determine whether there is a change point within the three pixels following the pixel position of interest on the reference line and its color.

To encode the second line, the second line 403 in FIG.
When input as the image signal 121, the line buffer memory At02 is in the write mode, and the line buffer memory B103 is in the read mode.

That is, the first line 402 written in the line/< rough memory B103 during the coding operation of the first line 402 becomes the reference line, and the newly input second line 403 becomes the coding. Then, the same operation as in the first line is executed.

Each signal waveform on the second line 403 is shown in section T2 in FIG. The data on the first line 402 is read.

The above is the specific operation of the circuit block shown in the first diagram.

Next, the circuit block shown in the second diagram will be explained.

201 is a symbol detection circuit, and as shown in the figure, signals 129,
130, 131, and detects the necessary symbols aO+a1+a2, bl, b2, etc. in the MMR encoding method. The definitions of these symbols are as follows.

ao = pixel on the =-ding line that serves as the starting point for encoding.

a1 = the first change point (pixel) on the coding Φ line to the right of a□.

a2=first change point (pixel) on the coding line to the right of a1.

b1 = A changing point (pixel) on the reference line to the right of a□, the opposite color to aQ, and the first changing point.

b2 = first change point (pixel) on the reference line to the right of b1.

However, the right here means the same as the relationship between the left and right of each pixel shown in FIG. 4, for example.

Next, 202 has a B register, and the clock 134 uses the changing point signal b1 shown at 222 in FIG. 2 as input data.
The 3-bit shift signal is sequentially shifted in by
It is a register.

Therefore, the change point signal b detected by the symbol detection circuit 201
1 is held over three clock periods, and the position of the change point signal b1 relative to the pixel of interest can be determined.

203 is a run length counter, which usually corresponds to pixel a
It is a binary counter that counts the number of pixels (run length) from O to pixel a1 or from pixel a1 to pixel a2, and has a 12-bit output.
This counter can count up to 559.

ff', the signal indicated by 228 in FIG. 2 is the lower 6 bits of the count value output of the run-length contention counter 203. Further, the signal indicated by 227 in FIG. 2 is the upper 6 bits of the count value output from the run-length counter 203.

204 is a ROM table A, which mainly stores bus mode (P mode) codes, and vertical mode (V mode) codes.
This is a ROM (read only memory) that stores the codes and the number of bits (code length) of each code, and can output the codes and code lengths in parallel according to the input input.

Further, 205 is a ROM table B, which is a ROM that mainly stores make-up codes and code lengths for the horizontal mode (H mode), and selects the code and code length to be output using the signal 227 as an address. Output.

Reference numeral 206 is a ROM table C, which is a ROM that stores the H mode termination code and code length, and selects and outputs the code and code length to be output using the signal 228 as an address.

207 and 208 are latch circuits that temporarily store the make-up code and code length output from each of the ROMs. Further, 209 is a latch circuit that temporarily stores the terminating code and code length output from the ROM.

210 is a buffer memory for sequentially receiving the code and code length in the latch circuit C209 and temporarily storing it.

Here, I will explain the encoding rules of the MMR method a little more. In this encoding method, the symbol a defined as described above is
o, al + A2 are on the coding O line, and likewise symbols b1 and b2 are on the reference line. And each of these symbols aO, al, A
2(7) Group and bl.

Based on the relative position (distance gI) of the group b2, it is specified that the encoding mode is uniquely selected from the following three modes and encoding is performed.

(1) Pass mode (P mode) When b2 is to the left of al (there is only one generation code) (
2) Vertical mode (V mode) When la 1 b・Follow the length code table) Format: )i+M(a□al)+M(a1a2) Here, H is the code indicating H mode, M (ao a 1) is the run length code of white or black 1aoaxl, M (
ala2) is black or white 1a1a210 run length Φ
It is a code.

However, if two or more of the above (1), (2), and (3) are satisfied at the same time, (1) P%-do > (2) V%-do > (3) H Priority is given in order of %-code.

The code determination circuit 21 controls this priority output operation.
2, and the code determination circuit 212 selects the latch.

Next, the operation of encoding the first line image 402 in FIG. 4 will be described.

First, in this embodiment, at the time t□ shown at 320 in FIG.
Let be the encoding start time.

That is, time 1 (,) is the time when the first pixel of the reference line and the coding line appears at the C4 output of the C register 110 or the A4 output of the A register 108 in FIG. 2, respectively.

That is, at time 1 to, C register 110. B register 1
The respective outputs of the 09 and A registers 108 output the first pixel of the reference line and the coding line and the states of three pixels in parallel to the first pixel. Also, aO
is the initial value " as shown in 221 AO (a□) in Figure 3.
It is set to O゛ (white pixel = virtual).

The run range counter 203 starts from the initial value O to the time to
Thereafter, the image clock 134 starts counting.

The count value output of the counter 203 at each time is
It is shown at 322 in the figure.

At time t'o, the signal 129-4 in FIG.
' is not set, that is, there is no change point in the A4 output of the register 108 (A shift) in FIG.
The B4 output of register 109 also has no conversion point. Therefore,
Since there is no factor that generates a code, the count value of the run-length counter is simply incremented by 1 and the process advances to the next time t1, but the state at time t1 is the same as that at time 1 (, ).

Next, when proceeding to time t2, the signal 129-4 in FIG.
°° is standing. This means that A register 1 in FIG.
The A4 output of 08 becomes 1, indicating that a change point exists at that position on the coding line. Since this change point is the first change point to the right of the current starting point aQ (corresponding to a later time), the symbol detection circuit 201 in FIG. 2 determines that it is the symbol a1.

Note that the detection state of this symbol a1 is stored as Fal.

At this time t2, 130-1 to 130- in FIG.
When I look at number 4, none of them have 1 pa. This means that there is no change point b1 within three times from time t2. Further, when the symbol detection circuit 201 detects bl, the symbol detection circuit 201 shifts the bl to the B'' shift register 202 so that it does not disappear for a period of time 3.

The symbol detection circuit 201 also has a circuit for storing that bl has already been detected.

Due to these, in this case, there is no change point pixel b1 within 3 pixels on the left and right of change point pixel a1, and
Until then, it can be determined that there is no bl (therefore, there is no b2 either). Therefore, although al was detected at time t2, P
It is determined that the conditions of mode (b2 must already be detected) and V mode (Iatbtl<3 is the condition) are not satisfied, and therefore the mode becomes H mode.

At this time, the value of the run length contest counter 203 is as shown in FIG.
As shown in 22, the number of pixels from aQ to al is shown, and “2
It is ゛′. Also, the run length color is initially set °l
OII = remains white. Therefore, the ten-length value, color, etc. are given to the ROM table C206 by the output 228 of the run-length counter 203, and the corresponding code and code length are output from the ROM 206. In this case, a code of “white run 2'' is output, that is, M
(aoal)=White 2.

At this time, it is determined that it is the first code of the H mode, and the code ``001'' indicating the H mode is controlled to be output at the same time as the code ``0111'' of white run 2, that is, at one clock. Further, the code length is also output as a binary number or the like at the same time.

Next, the run length contest counter 203 is set to an initial value of 1 (O
Note that this is not the case).

The count moves from pixel a1 to pixel a2. However, pixel a1
That is, at time t2, only preparations are made to set the initial value, and the initial value is set in the counter and the count advances from the next time t3. Furthermore, from this time t3, the color of AO is also inverted. (Time t2="0" → Time t3="'
l''), and thereafter, as time 1n advances, a change point appears at time t4, when the A4 output of the A register 108 becomes "1'".The symbol detection circuit 201 detects that the change point a1 has already passed. The symbol detection circuit 201 remembers that it has been detected (Fa1=1).
Therefore, it is determined that a2. Note that this detection state of a2 is stored as Fa2. Now, at time t4, the value of the run-length counter 203 is 2, and AO=°"1"=black.Also, since it has already been determined that the mode is H mode at time t2, a2 is detected, the state of the reference line, that is, 131-1 to 131-1 in Fig. 3 is detected.
There is no need to refer to 131-4 and 130-1 to 130-4 in Fig. 3. Although it is not a wooden case, even if there are bl, b2, etc. on the reference line, it is controlled to be ignored. be done.

As a result of the above, the code and code length of M (a 1. a 2) = black ° "21-" are output in the same way as for M (ao, ax). In this case, M (aO, al)
Unlike in the case of , the code "001°" indicating the H mode is controlled not to be added.

Next, after time t4, ie, at time t5, the run-length counter 203 is set to the initial value 1. or,
AO (=ao) is inverted.

Then, the change point a2 at time t4 is the starting point aO of the next mode.
considered to be.

Through the above operations, the code generated by encoding the first line 402 becomes as shown at 501 in FIG.

Furthermore, at time t30 in FIG. 3, the run-length counter value is 9, and at this time, the symbol f1 (=at) is detected, but there is a change point do1 after two pixels on the reference line. At time t30, it is determined from the output 130-2 of the B register 109, the output 131-2 of the C register 110, etc. in FIG. Therefore, the condition 1atbtl<3 is satisfied, and it is not P mode (b2 is required).

By definition, it is determined to be V mode and VL (2) Code (
(al is located two pixels to the left of bl) is output.

At this time, the H mode run length/white 9 code could have occurred, but according to the definition of priority between each mode mentioned earlier, the ■ mode became the valid code, and the H mode code becomes invalid. Due to the occurrence of the Zara V mode code, the run length counter 203
The count value up to time t30 is cleared and controlled to be newly preset to 1. Also, ■
After the mode code is generated, the color of the origin aO symbol is inverted. (However, the ■ mode code is generated at the same time as the change point detection of the a1 symbol (time t30).) Also,
Although not explained so far, when symbol b1 is detected before symbol a1, the detection signal of symbol b1 is shifted into the register as an input signal to the B register 202, and the detection signal of symbol b1 is shifted into the register as an input signal to the B register 202. , the output of the B register 202, B
It shifts in the order of 5 → B6 → B7, and disappears after that. Further, when the symbol b1 has already passed the B4 output of the B register 109 but no code is generated yet, this fact is stored as shown by the output Fbl of the storage detection circuit 201.

Next, specific circuits of each functional block of the circuit block shown in the first diagram will be explained.

The virtual change point generation circuit Al0I and the virtual change point generation circuit B105 in FIG.
2 is a flip-flop, 703 is an AND gate, 704
is an OR gate, and 705 is an inversion circuit (inverter).

The operation of the circuit shown in FIG. 7 is shown in the timing chart of FIG. 8. That is, the numbers of the parts in FIGS. 7 and 8 correspond to the numbers in FIGS. 1 and 3. However, Figures 7 and 8
The signal indicated by 701 in the figure is, for example, the position (timing) of the last pixel in one line obtained by decoding the count value of the memory address φ counter 111 shown in the first figure.
This is a signal indicating. That is, at the time when the signal 701 is generated, the flip-flop 702 is set to the same color as the last pixel of the coding line in synchronization with the clock 134, and after that time, that is, after the horizontal synchronization signal 136-2 is deenergized, the flip-flop 702 is Assume that the Q output of is 122 signals.

Before this time, while the horizontal synchronizing signal 136-2 is being output, the image 121 is output as the 122 signal.

The selector 104 in FIG. 1 is realized by the circuit shown in FIG. 9, in which 902 is an AND gate, 903 is an OR gate, and 904 is an inverter. 123,1 in Figure 9
24 is the output 12 of the line buffer memories A and B in FIG.
3°124, but the signal 901 in FIG.
This is a select signal whose level is inverted for each line, and is generated by the horizontal synchronizing signal 136-2 in FIG. The output to signal 125 is switched by the select signal 901.

Change point detection circuit A106 and change point detection circuit B in Fig. 1
107 is a circuit of the same type, and FIG. 10 shows a typical configuration of the change point detection circuit B107.
4 is an inverter.

That is, as shown in the timing chart of FIG.
), it is detected that the colors of adjacent pixels are different, and this is used as a change point signal.

Next, specific circuits of various functional blocks in the circuit block of FIG. 2 will be explained.

FIG. 11 is a circuit for detecting the symbol a1 or a2 on the aforementioned coding line and the FAL signal indicating that the aforementioned al has been detected, and is the symbol detection circuit 2 shown in the second diagram.
In the 0 diagram in 01, 1102 is a flip-flop, 1
104 is an AND gate, and 1105 is an inverter.

Now, the numbers of each part in FIG. 11 correspond to the numbers in FIG. 1, etc. The signal shown at 1101 in FIG. 11 returns the flip-flop 1102 to its initial state (i.e., Q output;
This is a control signal that prohibits the Q output from being set to "'o") or Q output = "1", and is normally at the "1" level.

The same applies to the RESET signal 1103. Here, when the change point A4 (129-4 signal) arrives first, A4
=゛1'', in this case, the flip-flop 1102
Since Q output = "1" and control signal 1101 = "1", al = "°1'° is output and symbol a1 is detected. This a1 detection signal causes flip-flop 110
2 is set, Q output = “1”, and it is remembered that al has already been detected (that is, Q output = F a 1 =
"1"), and in this state, when A4="1", a2=1°, and symbol a2 is detected.

Next, the circuit for detecting the symbol bl etc. is shown in FIG. 12, in which 1201 is an exclusive OR gate,
03 is a flip-flop, 1204 is an AND gate, 1
205 is an inverter. The number of each part is numbered 11th.
This is the same as the case shown in the figure. However, aQ can be bl.
Exclusive or game due to the condition of opposite color) Change of reference line at 1201 and a.

The circuit uses the signal obtained by exclusive ORing with the signal. The circuit shown in FIG. 12 is included in the symbol detection circuit 201 shown in FIG.

A specific configuration of the run length counter 203 shown in FIG. 2 is shown in FIG. 13. First, as mentioned above, the run length counter 203 is a 12-bit binary counter, and the counting range of the counter 203 is from 0 (decimal) to 25
60-t (2559 in io system), and the counter 203 has a preset function, a clear function, etc.
C., type name 74F163, etc.

Furthermore, the count value output of the counter 203 is decimal number 2.
Circuit 1 that detects a book that is 559 and generates an MKI signal
301 and the value obtained by decoding the lower 6 bits of the output is 1
The circuit 1302 detects that the decimal number is "63" and generates two signals at M.

Furthermore, “O” is set as a value using the preset function.
(decimal number) or °°1°' (decimal number) can be selectively preset.

The manner in which the run length φ counter 203 moves will be explained. First, for each coding line, the initial value "o" is preset (or cleared) at a position outside the left edge of the image. Next, within the image area, the count is sequentially advanced pixel by pixel, and the following values or three states are set: At this time, the counter 203 is returned to "1" by the preset function.

That is, (1) When the change point a1 or a2 is detected.

([2) When the count value reaches 2559.

(3) When a P-mode Φ code or a V-mode code occurs, however, if the changing point a1 is set to a2 on a virtual pixel outside the rightmost end of the coding line according to the rules of the encoding method, At the time of detection, the counter value is returned to "O11".

Next, the configuration of the ROM table A204 in FIG. 2 will be described. The 1ROM table A204 is used to generate a total of eight types of codes, P mode and V mode, and their code lengths. As is clear from the configuration principle of this embodiment and the above explanation, the configuration described here is based on the relative relationship between the changing point positions of the coding line and the reference line, and especially when the changing point b2 on the reference line is at the B register 1.
09, or when the change point a1 on the coding φ line appears as the A4 output of the A register 108, the state of the symbol detection circuit 201, the A register 108, the B register 109, The configuration is such that the status of each output of the C register 110 and the B register 220 can be determined simultaneously and in parallel. Therefore, the combinations of the word output states are naturally finite, and at the time of judgment, they can be treated as static states. Therefore, since the P mode or V mode code and code length to be output for each combination can be determined, it can be configured as the ROM table.

The specific contents of the ROM table are too redundant here, so as an example, Figure 14 shows a case where a P mode code and code length are generated by a logic circuit equivalent to a ROM. Among them, 1409 is an inverter, 1410 is a timing circuit, 1411 is a Nant gate, and 1412 is a NOR gate. That is, 14 in Figure 14.
The signal indicated by 01 is a signal indicating that the change point b2 has been detected on the reference line in the symbol detection circuit 201 of FIG.

That is, this means that the B4 output of the B register 109 in FIG. 1 has a changing point as b2. Similarly, the a1 signal indicated by 1402 in FIG. 14 is the a1 change point as the A4 output of the A register 108 in FIG. Furthermore, the FAL signal shown at 1403 in Fig. 14 has reached the second level by the current time.
This is a signal indicating that the graphic symbol detection circuit 201 has already detected the change point as al.

The logic circuit shown in FIG. 14 means that at the time when b2 is detected, the P mode is determined because the al or Fal signal is not "true". That is, it means that there is no a1 change point after the starting point aO until the time when b2 is detected. That is, on the image, there is no a1 change point between the starting point aQ and directly below the b2 change point.

Therefore, by definition, it is in P mode. 140 in Figure 14
4 is a P mode detection signal, 1405 is a specific code of P mode, and 1406 is a binary number representing the code length of the P mode code. Further, 1407 is a signal indicating that a P mode code has been generated, which is 0 or more, which is a method for determining P mode, but the same method can be applied to ■mode. The ROM table A204 is configured by this method.

After all, the code and code length of the P mode or V mode are determined by applying the status signals of each register as input data to the ROM table A204 in FIG. 2 based on the method described above at the time when the b2 or a1 symbol is detected. In some cases, it is generated instantaneously at a time of 1 clock.

ROM table B2O5 and ROM table C in Figure 2
Since the ROM table 206 has a similar structure, the ROM table 0206 will be explained with reference to FIGS. 15 and 16 as a representative.

First, 206 is a ROM with at least 11 bits of address input and 21 bits of parallel output;
The human power corresponds to the 228 signal in FIG. That is, they are the lower 6 bits of the run length counter 203 in FIG. In addition, 1502 (manual power) in FIG. 15 (7) is a signal specifying the color of the run length, and in this example, "white=O1 black=1".

Also, 1503 human power is a code indicating H mode (=OO1)
This is a signal that specifies whether to add or not. In this example, required = 1
, Unnecessary - 〇. That is, if 1503 manpower is 1, H
The code (001) added to the first run length code of the mode code is output in one clock.

Reference numeral 1504 is an enable signal that controls whether the output of the ROM 206 is enabled or disabled. 150
7 manpower is EOL<1507 manpower is EOL+ 1.150
8 are address inputs that control the reading of each EOL 10, and by inputting pulses to these inputs, the delimiter code of the corresponding line is read. or,
1505 is the code output of the address specified by the input and is 1
Similarly, 506 is the cord length of the needle.

FIG. 16 is a diagram showing the correspondence between the addresses AO to A10 in FIG. 15 and the stored contents (data).

The code determination circuit 212 of FIG. 2 is specifically explained with reference to FIG. 17. In FIG. 17, 1706 is an AND gate;
is an inverter.

As can be seen from the principle of the coat generation method in this example,
ROM table 204 and 205 or 206 shown in the second diagram
etc., P mode.

In the stage before each of the needs of mode (1) and H mode is finally determined as the code to be generated, two or more may be output from the ROM table at the same time. But 2
As mentioned above, the above codes are defined by bond priority. FIG. 17 shows a circuit for determining the code to be uniquely generated according to Hiro's definition.

In other words, if P mode, ■ mode, and H mode codes can occur at the same time, the need for the mode that has acquired priority will eventually occur based on the order of P mode, ■ mode, and H mode, as described above. Needs in other modes are invalidated and do not become a 1-occurrence code.

The signal 1708 is a mode signal for selecting whether to use the present encoding circuit for the MR method, that is, -dimensional encoding, or for MMR or MR two-dimensional encoding, and executes -dimensional encoding. When performing two-dimensional encoding, the level is L. On the other hand, when two-dimensional encoding is performed, the level is H.

Therefore, when performing -dimensional encoding, the generation of P mode and V mode is prevented, and only the H mode, ie, the code representing run length, is always valid.

Next, the roles of the latch A207, latch B2O3, etc. in FIG. 2 will be described. Latch A207 and latch B2O
Reference numeral 3 denotes a circuit for temporarily storing the H mode make-up code and code length that are generated during coding until it is determined whether the H mode is valid or invalid. If it is determined that the H mode is valid, the contents of the latch are transferred to the next stage circuit.

Taking the functions of the latches A207 and B2O3 in FIG. 2 as an example, a case where the run length in which the make-up code is generated is long will be explained, for example, with run length=2972. At this time, according to the encoding regulations, the code is divided into a total of three run-length codes, two make-up codes and one terminating needle, and output as follows.

That is, Make-up code 1 = Run length 2560: I-do (common for white and black) Make-up code 2 = Run length 384 code (white or black) Terminating code = Run length 28 code (white or black) Like this When one run length is represented by multiple codes such as 2560+384+28=2972, first, the count value of the run length counter 203 in FIG. 2 is 63+64XN (N=0.1.2...・
If the A4 output of the A register is not at the a1 change point at that point, it is predicted that a make-up value will occur next, and M: the value of the upper 6 bits of the counter 203 (H R
It is output from the OM table B2O5 and temporarily stored (:latched) in the latch B2O3. Next, the previous value count value is 6
The contents of the latch B2O3 are updated every time N advances by 4 (that is, each time N advances by 1 in the formula 63+64XN).

Then, the value of the run length counter 203 is 2559.
(In other words, if the change point a1 is not detected at the time when N = 39 in the formula 63 + 64 Read the code and code length of run length 2560 and latch A2.
Temporarily stored in 07. At the same time, the mnemonic contents of latch B2O3 are temporarily invalidated. Further, the count value of the run length counter 203 is returned to the initial value 1. Subsequently, as the count progresses, storage of the make-up code and the like in the latch E208 is resumed in the same manner for each of the above-mentioned formulas 63+64XN.

When the change point a1 is detected, the competitive relationship with other P mode or V mode is determined, and when the H mode is determined, the run length counter 2 at the time of the change point a1 is determined.
The termination code and code length of the run length indicated by the value of the lower six bits of 03 (0 to maximum 63) are temporarily stored in latch C209. Furthermore, as already described above, the contents of latch A207 and latch B2O3 also become valid.

However, if V mode etc. occurs at the time of change point a1, H mode itself will not occur, and naturally latch A20
7 and the contents of latch B2O3 are invalidated, and the contents of latch C
209 instead of the above-mentioned terminating code.
Mode code is latched as valid code.

Makeup code 1 and makeup code 2 above
FIG. 18 shows a circuit for controlling the generation and storage of the data, etc., and this circuit is included in the timing circuit 112. Timing chart of this circuit (: run length is as described above)
2972) is shown in Figure 19.
801 and 1802 are flip-flops, 1803 is an AND gate, and 1804 is an inverter.

MKI and MK2 are signals output from the 2559 detection circuit 1301 and the 63 detection circuit 1302, respectively, of the run length counter 203 shown in FIG. The flip-flop 1802 is set by the input of the MK2 signal and generates the MK2 presence signal, and the flip-flop 1801
is set by the input of the MKI signal and generates the MKI presence signal. Note that the flip-flop 1802 is reset by inputting the MKI signal.

With the above configuration, the run length counter 203
When the count value becomes 64 or more, the MK2 signal becomes high level, and when the count value becomes 2560 or more, the MK2 signal becomes high level.
Only the KI presence signal or both the MK2 presence signal and the MK2 presence signal become high level. Depending on the levels of the MKI presence signal and MK2 signal, it is possible to determine whether the code representing the run length is only a termination needle or a combination of termination needle and makeup code, and whether the number of makeup codes is 1 or 2. You can determine if there is. Therefore, H
When generating a code in this mode, the backing circuit 211 determines the levels of the MKI present signal and the MK2 present signal, selects the valid one among the three latches A, E, and C, and outputs the latch data. Take in.

In this way, when a make-up poo occurs, by predicting the occurrence of the code at least one hour in advance and sending the code to the temporary memory circuit (latches A, E), the change point a1 can be predicted. This is extremely effective in terms of circuit configuration since it has the effect of preventing an increase in the number of output needs and the number of bits to be processed at the same time.

That is, by temporarily storing the required make-up code and code length among the numbers counted by the latch A207 and the latch B2O3 range counter 203 before determining the H mode, the terminating code and code length are stored when the H mode is determined. Since only the code length needs to be processed, all the H-mode codes to be output at the time of al detection are available, and the subsequent encoding operation can be executed without delay.

207, 208, 209 latches A, E.

The order in which the contents of C are sent to the next stage circuit is latch A207>
It is controlled so as not to disturb the order of latch B2O3>latch C209 (: 2 to buffer) (if the contents are invalid, it is omitted or ignored).

The reason why the contents of latch C209 are temporarily stored in buffer memory 210 is because the next encoding operation starts from the time after the encoding mode is determined, and the next encoded data is stored in latch C209 from the ROM table for several clocks (minimum (Flock) may be entered. Therefore, after the mode is determined, the contents of the latch C209 are sent to the buffer memory 210 so that the next encoded data can be latched, and then output from the buffer memory 210 to the subsequent stage at a certain timing.

Next, a special case in which the change point a1 and the change point a2 are set on the same pixel according to the encoding method will be described.

FIG. 20 illustrates the above case. That is,
In Figure 20, 2001 is the reference line, 2
002 is a coding line. Also, 2003 is the final pixel of the coding line, and 2004 is the virtual change point (
pixels).

Now, in FIG. 20, if it is assumed that the starting point aQ is at the position shown in the figure as a result of encoding from the left, the next need to be generated is as shown in FIG. 21.

[H mode code + White 12 termination need, Jukuro 0 termination code]. Here, the code in Figure 21 (1) can be treated as one need at the time of change point a1 by the above-mentioned means, and there is no problem. However, the need in Figure 21 (2) originally changed at change point a2. This is a need that should occur at the time of the change point a2 when the point a1 is different from the time. However, in this case, it is clear that the change point a2
As such, it is not detected by the symbol detection circuit 201 or the like.

Therefore, in this case, the following processing is performed by the circuit shown in FIG. 22 provided in the symbol detection circuit 201. FIG. 23 is a timing chart of the operation of this circuit. In FIG. 22, 2201 is a signal indicating that the image has entered the virtual area (
2202 is an a1 change point detection signal, and 2203 is a signal indicating up to the generation of the first termination code in H mode. The signals 2201 to 2 are monitored by the AND gate 2207.
By taking the AND of the 203 signals, the state shown in Figure 20 is detected and the 1.2204-1 signal is created (i.e., the time is a
1), first output the code shown in FIG. 20 (1) using the method described above. Next, predetermined processing such as clearing the run length counter to O is performed, and the 2204-1 signal in Fig. 22 is changed to D.
The black 0 in FIG. 21 (2) is generated by the 2205-1 signal delayed by one time in the delay circuit 2208 consisting of a flip-flop.
generates the termination code.

The backing circuit 211 in FIG. 2 receives as input the code and code length obtained by the method described above, and the length of each successive code (the number of bits of the code) is not constant, however, the longest one is Even if the H mode code (=001) is added, the number of bits is 16 bits).This is a circuit that sequentially collects data in units of 16 bits, and in this embodiment, each 16 bits are passed to the next external circuit in parallel. It is.

The signal 238 in FIG. 2 is a need compiled into 16 bits by the backing circuit 211, and the signal 239 is a signal for notifying this fact to the next stage external circuit. Note that the backing circuit 211 is a code length addition circuit and a bit shifter.

This can be easily realized by combining well-known circuits such as multiplexers and latches.

RTCI' indicating the end of lA''-di in δ', Re t
urn to control) signal details. In the case of the MMR method, RTC code=EOL code×2 times. That is, the RTC signal is (OO0000000001
)X2=00000000ooot, ooooooo
It is expressed as oooooi. Furthermore, in the unembodied embodiment, the structure is such that up to 16-bit code can be output in one clock time, as described above. Therefore, in order to output the RTC signal, by monitoring the vertical synchronization signal 136-1 shown in Figure 3, etc., the end of lA''-ji is detected, a balloon of 2 clock times ([2 times)] is generated, and this Ballun (
: Shown in FIG. 15) By giving the EOL code and code length as the address signal 1507 of the ROM table C206, write the EOL code and code length in the corresponding address of the ROM table, and output the RTC code as the code for the above-mentioned image. You can get it by following.

Next, Table 1 lists the differences between the three encoding methods described above.

Therefore, the encoding method of the MH method is almost the same as the case where the H mode of the MMR method described above is repeated, but differs in the following points.

That is, (1) the H mode code (001) is not required in the MH method (:2) it is not necessary to pair white runs and black runs in the MH method (3) the EOL code is inserted for each line in the MH method (4) Differences in RTC and (X) in the case of the MR method Dimension lines are the same as the MH method (2) Two-dimensional lines are the same as the MMR method (3) Line separation is EOL + 1 = OOO0000000011 or EOL + 0 = 0000000000010 (4) RTC
Difference (5) Due to the K parameter, one-dimensional lines and two-dimensional lines coexist.

After all, switching between the three encoding methods can be easily realized by controlling the operation of the circuit for the MMR method described above using a method selection signal for the MR method or the MH method.

First, Figure 24 shows an example of a circuit that controls lines, breaks, and code differences. In Figure 8, 2407 is a line counter;
2408 is Nante gate, 2409 is AND gate, 2
410 is an inverter. That is, 2401 in FIG.
is a pulse signal at time t-1 shown at 320 in FIG. 3, which is repeated for each coding line, and no code is generated at time t-1 due to image encoding. This t-1
The time pulse signal is obtained by decoding the value of the address counter 111. Further, 2402 and 2403 are encoding method selection signals from outside the circuit of this embodiment, such as a CPU, which specifies the encoding method. Also, the 136-2 signal is 1 in Figure 3.
36-2 signal and therefore the Kil counter 240
7 is a signal 136- indicating the progress of the variable meter in the MR method.
2 is counted and monitored as a line reference counter.

Signals 2404 to 2406 obtained by the logic in FIG.
Input the address of ROM table C206 in Figure 2 (:
1507 to 1508 in Figure 15), each specifying a specific address, and outputting the code and code length required at the specific address, the desired line can be set.・Get the delimiter/code.

Furthermore, the one-dimensional line encoding method of the MH method is described in the 17th
The selection signal 1708 may be used to control the mode determination circuit of the MMR method shown in the figure so that the H mode can always be given priority.

Also, in the MH method, the H mode code (o o B
This is also achieved by setting the address signal A7 of the ROM table C206 to O.

The difference in the number of EOLs in NuRTC is ROM table C.
This is achieved by varying the number of pulses applied to 206 depending on the mode.

In this example, as shown in Fig. 3 (] image)
Although it operates in synchronization with the clock 134, it is not related to the interval (period) of the clock. Therefore, as shown in FIG. 25, a pause period can be easily provided between images or lines by masking the clock 134 with an image gate signal.

That is, in FIG. 25, 2501 is the image gate signal "0".
This is a signal indicating that the operation is suspended during the pare level. Further, 2502 is the gate signal 2501 and the clock 13.
2502, and if this clock 2502 is sent to the actual internal circuit of this embodiment instead of the aforementioned clock 134, the state of this embodiment can be changed only by the clock signal. Since the state can be changed, the shaded area in FIG. 25 is clearly in a rest state.

With this pause control, for example, the output speed of the image signal from the source of the image signal to be encoded is not limited by the operation of the encoding circuit. Nu.

Conversely, even if the image signal of one page is output intermittently, for example, when the image source is an image file with a disk, the encoding circuit will encode the image signal in synchronization with the intermittent output. Operations can be performed intermittently. Therefore, the image signal from the output source can be sequentially encoded without requiring a large buffer memory for time adjustment between the image signal output source and the encoding circuit.

26 and 27, a method for supplying images to be encoded to the circuit of this embodiment in parallel format will be described. That is, 2601 in FIG. 26 is a parallel-to-serial change shift register that can input 8-bit parallel data and output it to 2602 as 1-bit serial data.

As shown in FIG. 27, after loading the image signal to be encoded into the register 2602 as 8-bit parallel data,
A serial shift is performed using a clock to obtain a serial image signal 2602 as shown in FIG. At the same time, the number of clocks during the serial shift is counted to generate a gate signal 2702 indicating the section of the actual data, and a clock 2702 corresponding to the actual data can also be obtained in the same way.

As described above, the signals as shown in FIG. 27 are in a format that can be encoded as described above in this embodiment by the pause method described in FIG. 25. The operation for parallel input of this image is Cp
This is extremely effective when an image is provided by u, etc.

In the above embodiments, MH, MR, and MMR encoding has been described, but it goes without saying that other encoding methods can also be applied. Further, the image signal to be encoded is inputted from a device that photoelectrically reads an original image, a combinator, etc., and the encoded code is transmitted to a remote location via a transmission line or the like, or is stored in an image file. Although the present invention has been described above based on preferred embodiments, the present invention is not limited to this configuration, and various modifications can be made within the scope of the claims. Table 1 [Effects] As explained above, according to the present invention, in two-dimensional encoding, the encoding codes of each mode can be generated and used at the same time, and these are selectively output in accordance with the priority order. As soon as the mode is determined, the optimal encoding code can be output immediately.
Encoding operations can be performed without delay in inputting image signals.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of an encoding device to which the present invention is applied, FIG. 3 is a timing chart showing the encoding operation, and FIGS. 4, 5, and 6 are reference line 7 is a diagram showing a configuration example of a virtual change point generation circuit, FIG. 8 is a timing chart diagram showing the operation of the circuit shown in FIG. 7, and FIG. 9 is a configuration example of a selector. 10 is a diagram showing a configuration example of a change point detection circuit, FIGS. 11 and 12 are diagrams showing a partial configuration example of a symbol detection circuit, and FIG. 13 is a diagram showing a configuration example of a run length counter. 14 is a diagram showing a configuration example of an equivalent circuit of ROM table A, and FIG. 15 is a diagram showing a configuration example of an equivalent circuit of ROM table C.
FIG. 16 is a diagram showing an example of the contents of ROM table C, FIG. 17 is a diagram showing an example of the configuration of the code determination circuit, and FIG. 18 is a configuration example of the make-up code generation and storage circuit. 19 is a timing chart showing the operation of the circuit shown in FIG. 18, FIG. 20 is a diagram showing the relationship between the beam farenne line and the coding line, and FIG.
Figure 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, Figure 23 is a timing chart diagram showing the operation of the circuit shown in Figure 22, and Figure 24 is a diagram showing control of generation of line separation codes. Diagram 25 showing an example of the configuration of a circuit for
26 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 is a diagram showing a configuration example of a circuit that serially outputs parallel input of an image signal, and FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26. It is a chart diagram, lo
t and 105 are virtual change point generation circuits, 106 and 107
is a change point detection circuit, 108 to 110 are registers, 111
is an address counter, 201 is a symbol detection circuit, 203 is a run length counter, and 207 to 209 are latches. Applicant: Canon Co., Ltd. Figure 7: Figure 8a Figure 52 Figure 5tO Figure 1/Figure 7215J Port 75 Figure dZ Shioraku/Otsu Figure M-de Hood + White 1?・9-Mineido Cordona Black 0-
Terminate Food (1)
(Figure 2-24 VEN Pause Pause

Claims (1)

[Claims] Means for serially capturing the image signal of the reference line in synchronization with the serial input of the image signal of the encoding line, counting the number of pixels between conversion points of the image signal of the encoding line, and generating the encoding code based on the counted value. a first generating means for generating an encoded code; a second generating means for monitoring a correlation between an image signal of an encoded line and an image signal of a reference line and generating an encoded code based on the correlation; 1. A two-dimensional encoding device for an image signal, comprising: selection means for selecting an encoding code to be output according to a predetermined priority order when encoding codes can be generated simultaneously from the means.