JPS623142U - - Google Patents
Info
- Publication number
- JPS623142U JPS623142U JP9397685U JP9397685U JPS623142U JP S623142 U JPS623142 U JP S623142U JP 9397685 U JP9397685 U JP 9397685U JP 9397685 U JP9397685 U JP 9397685U JP S623142 U JPS623142 U JP S623142U
- Authority
- JP
- Japan
- Prior art keywords
- delay circuit
- delay
- pass filter
- modulator
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図はこの考案の一実施例によるＭＳＫ変調
器を示すブロツク回路図、第２図は第１図の動作
を説明するための動作波形図、第３図はＭＳＫ変
調器の原理を示すブロツク回路図である。
図中、１３は遅延回路、１４は排他的論理和回
路、１５は低域フイルタ、１６はモニタ端子であ
る。なお、図中、同一符号は同一、又は相当部分
を示す。
FIG. 1 is a block circuit diagram showing an MSK modulator according to an embodiment of this invention, FIG. 2 is an operating waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing the principle of the MSK modulator. It is a circuit diagram. In the figure, 13 is a delay circuit, 14 is an exclusive OR circuit, 15 is a low-pass filter, and 16 is a monitor terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
タル周波数変調する変調器（ＭＳＫ変調器）にお
いて、２波の搬送波のうちいずれか一方を遅延さ
せる遅延回路と、この遅延回路により遅延された
遅延搬送波と他方の搬送波との乗算を行う論理回
路と、この論理回路の乗算出力の高周波成分を除
去する低域フイルタを備え、上記低域フイルタの
出力信号の位相誤差分が零となるよう上記遅延回
路の遅延量を調整するようにしたことを特徴とす
るＭＳＫ変調器。 A modulator (MSK modulator) that performs phase continuous digital frequency modulation of input data with a modulation index of 0.5 includes a delay circuit that delays one of two carrier waves, and a delayed carrier wave delayed by this delay circuit. The delay circuit includes a logic circuit that performs multiplication with the other carrier wave, and a low-pass filter that removes high-frequency components of the multiplication output of this logic circuit, and the delay circuit is configured such that the phase error of the output signal of the low-pass filter becomes zero. An MSK modulator characterized in that the amount of delay is adjusted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9397685U JPS623142U (en) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9397685U JPS623142U (en) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS623142U true JPS623142U (en) | 1987-01-09 |
Family
ID=30652128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9397685U Pending JPS623142U (en) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS623142U (en) |
-
1985
- 1985-06-20 JP JP9397685U patent/JPS623142U/ja active Pending
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