JPS6231508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device including at least a low-noise junction field effect transistor (hereinafter referred to as J-FET) suitable for high integration.

Conventionally, J-FETs have square-law characteristics and low noise characteristics that are not found in bipolar elements.
It is widely used in various fields including the acoustic field. However, the J-FET in a semiconductor integrated circuit in which the J-FET is integrated with an element such as a bipolar transistor is extremely disadvantageous in that it occupies a large area, unlike a single J-FET. J- for semiconductor integrated circuits with bipolar elements
One reason for incorporating FETs is that they enable lower noise compared to bipolar transistors. On the other hand, this J-FET is required to have the current required for other bipolar elements, and must also satisfy sufficient low noise performance. In order to satisfy this condition, a J-FET with low gate resistance and high transfer conductance (gm) is required, which requires a large area, and a J-FET with sufficient characteristics can be installed within a limited area within an integrated circuit. It is difficult to obtain. In other words, J-
FETs require about 15 to 20 times the area occupied in an integrated circuit compared to bipolar transistors, and multiple J-FETs formed in an integrated circuit occupy 20 to 30% of the entire integrated circuit, so the integrated circuit chip This results in an increase in area, which is extremely disadvantageous to the production of integrated circuits.

Figure 1 shows a back gate structure nchJ-FET integrated with a bipolar element (not shown), etc.
shows. J-FET built into integrated circuit
A surface channel, P-well backgate structure is adopted in which the formation of a channel region can be achieved without heat treatment to the extent that the base width of the bipolar transistor changes. 1 is a p-type silicon substrate, 2 is an n-type epitaxial layer formed on the substrate 1, 3 is a P-well formed in the n-type epitaxial layer 2 and serves as a gate, and 4 is a low resistance of P-well 3 P ⁺ channel stopper for eliminating contact and MOS effect, 5 and 6 are n ⁺ type source/drain formed in P-well 3, 7 is n channel connecting source 5 and drain 6, 8 is P ―well
The p ⁺ region connected to 3 becomes the surface gate.
9, 10, and 11 are source, drain, and gate electrodes; 12 is an insulating oxide film; and 13 is a p-type isolation region that isolates the epitaxial layer 2.

In the J-FET shown in FIG. 1, there is only one channel on the opposing surfaces of the source 5 and drain 6, that is, only on one side.
It is necessary to increase the channel width Z to obtain GM. Therefore, the area of the J-FET becomes larger, the gate region becomes larger, and the gate resistance becomes larger. When the gate resistance increases in this way, there is a problem in that thermal noise increases.

Therefore, FIG. 2 shows an example in which the mutual conductance per area of the J-FET is increased, that is, the area is decreased for the same mutual conductance. The plan view of FIG. 2a shows each region of the J-FET and the planar pattern of the source, drain, and gate wiring.

In FIG. 2, 21 is a p-type silicon substrate;
2 is an n-type epitaxial layer formed on the substrate 21, 23 is a P-well formed in the n-type epitaxial layer 22 and serves as a gate, and 24 is a P-well 23.
25 is an n ⁺ type source formed in the P ^- well 23, 26 is an n ⁺ type drain formed in the P-well 23, and 27 is a source. 25, n-channel connecting drain 26, 8 is P-well
23, p ⁺ connected to channel stopper 24
This is the surface gate region. 29, 30, 31 are source, drain, and gate electrodes; 32 is an insulating oxide film;
33 is a p-type isolation region that isolates the epitaxial layer 22. Also, x is the channel length.

In the example of FIG. 2, there is no need to provide a channel stopper on the right side compared to FIG. 1. Further, there are advantages such as there being no need to provide a P-well in the region surrounding the drain. Furthermore, when sources and drains are arranged alternately two-dimensionally, the drains are taken through the epitaxial layer, so there is no need to provide electrodes for each drain portion, which has the advantage of reducing the area.

However, in FIGS. 1 and 2, it is the surface gate that determines the transfer conductance, and the transfer conductance is determined by the channel length x. That is, in order to increase the transfer conductance, the channel length x must be shortened. However, if the channel length x is shortened, the gate resistance increases and thermal noise increases.

The present invention has been made in view of these problems, and the present invention increases the transfer conductance by implanting ions into the channel through, for example, a nitride film and forming the channel active region in a self-aligned manner, while also reducing the channel length. The feature is that by widening the front gate, gate resistance is reduced and noise is reduced.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a J-FET and a bipolar transistor formed in a semiconductor integrated circuit according to an embodiment of the present invention, step by step. An n-type epitaxial layer 102 with a specific resistance of 1 to 3 Ωcm is formed on a p-type substrate 101.
(Figure 3a). J-FET after oxide film formation
A hole is opened in the oxide film to separate the formation region 102a and the bipolar transistor formation region 102b.
The shaped diffusion region 103 is diffused to reach the substrate 101 (FIG. 3b).

Next, after removing the entire oxide film, a nitride film 104 is formed, an oxide film 105 is formed, and then the oxide film 105 and the nitride film 104 are selected in desired regions of the J-FET section 102a of the n-type epitaxial layer. With removal, layer resistance 2~4KΩ/mouth diffusion depth 3~4
A p-type back gate region (hereinafter referred to as P-well) 106, which is an island region serving as a μm gate, is formed (FIG. 3c).

After removing the oxide film 105 and forming an oxide film 107, a hole is opened in the oxide film 107 in a desired region in the P-well 106 to form a p-type region 108a for making low resistance contact with the P-well 106. At the same time, holes are opened in the oxide film and nitride film in desired regions of the bipolar transistor section 102b of the n-type epitaxial layer, and the p-type region 1 that will become the base region is opened.
08b (Fig. 3d).

Next, the oxide film 107 in the desired region of the J-FET part of the n-type epitaxial layer is removed, and the layer resistance under the nitride film is 3 to 5 KΩ/hole, and the diffusion depth is 0.5 to 1.0 μ.
Ion implantation and heat treatment are performed from the surface so that the n-type region 109 becomes a channel (FIG. 3e). At this time, p-type regions 108a and 108b
The amount of ions implanted into n-type region 109 is suppressed so that the concentration is lower than that of . Note that the n-type region 109
is formed extending from the p-type region 106 to the region 102b, and a portion 109' sandwiched between the nitride film 104 and the p-type region 106 serving as a back gate substantially becomes a channel region and the channel length is determined by this portion. Ru. That is, when forming the p-type region 106, the channel length is defined by the lateral extension of the region 106 below the nitride film 104, and the narrow gate length is determined when the channel region is formed by ion implantation. .

Next, after removing the oxide film 107, leaving the nitride film 104a on 109', an oxide film 111 is formed again, and this oxide film 111 is selectively removed. In the J-FET section, the n-type region 109
An n-type source region 112a and an n-type drain region 112b connected to are formed. Source area 112a
is formed in the p-type region 102, and the drain region 112b is formed in the n-type region 102a. At the same time, in the bipolar transistor section, the n-type emitter 11
2c and a collector low resistance portion 112d are formed (FIG. 3f). Thereafter, the oxide film is removed entirely and an oxide film 113 is selectively formed (FIG. 3g).

After this, the nitride film 104a is removed using the oxide film 113 as a mask to form a p-type surface gate region 114 with a higher concentration and shallower depth than the channel region 109 (FIG. 3h). Even though this gate region 114 is wider than the channel portion 109', the channel that actually operates is only the 109' portion.

Finally, after forming the oxide film 113',
In the FET part, the source and drain gates are opened, and in the bipolar transistor part, the emitter, base, and collector are opened, and the source, drain, and gate electrodes 115, 116 of the J-FET,
117 and the emitter of a bipolar transistor,
Base and collector electrodes 118, 119, and 120 are formed (FIG. 3i).

According to this embodiment, since the channel active region is formed by the self-alignment method, the channel length is shortened and the transfer conductance is increased.
As mentioned above, the channel length is becoming shorter, but since the surface gate can be formed wider,
The gate resistance becomes smaller and the thermal noise becomes smaller. Furthermore, when forming the channel region 109, the ion implantation is performed through the nitride film in the portion 109' that essentially becomes the channel, whereas the region 109 between the surface gate 114 and the source region 108a is formed by shielding the surface. Formed by direct ion implantation in the absence of any material, the concentration in this region is high and the source resistance is low, resulting in lower thermal noise.

Another embodiment is shown in FIG. In this embodiment, channel portions 109' are provided on the left and right sides. In other words, the transfer conductance has doubled. The left drain is connected to the drain 112b through the n-type heavily doped buried layer 121 as shown by the dotted line. That is, on the left side, there is no need to take out the electrode directly from the drain, and it has the advantage of increasing the transfer conductance per unit area.

As described above, according to the present invention, since the channel active region of the J-FET is formed by the self-alignment method, high transfer conductance can be obtained, and at the same time,
Since the source resistance is small, low noise characteristics can be obtained, and this device exhibits great industrial value in realizing semiconductor integrated circuits including high-performance J-FETs.

[Brief explanation of the drawing]

Figure 1a and Figure 2a are respectively conventional J-
A plan view of the main part of the FET, Fig. 1b and Fig. 2b are respectively sectional views taken along lines -' and -' of Fig. 3a, and Fig. 3a.
-i is a cross-sectional view of a process structure of an integrated circuit according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a final process structure of a J-FET portion of an integrated circuit according to another embodiment of the present invention. 102...n-type epitaxial layer, 104,1
04a...Nitride film, 105...Oxide film, 106...
...p-type back gate region, 108a...p-type region, 109...n-type region, 109'...channel region portion, 112a...source region, 112b
...Drain region, 114...Surface gate region.

Claims (1)

[Scope of Claims] 1. A first opening is formed in first and second coatings on a semiconductor layer of a first conductivity type, and
a step of forming an island region of a second conductivity type to serve as a back gate in the opening; and after forming the island region, removing the second film and forming a third film on the first film and the semiconductor layer. forming a first region of a second conductivity type in the island region through a second opening formed in the third coating; and removing a portion of the third coating to remove the first coating. a second region of the first conductivity type that becomes a channel from the island region to the semiconductor layer by ion implantation through the third opening and the first film; and removing the third coating and selectively removing the first coating,
A fourth film is formed on the remaining first film and the semiconductor layer, and a first conductivity type film, which becomes a source and a drain, is connected to the second region through a fourth opening formed in the fourth film. forming third and fourth regions, removing the first and fourth films, and forming a fifth region of a second conductivity type, which will become a surface gate, from the region where the first film has been removed onto the second region; A method for manufacturing a semiconductor integrated circuit, comprising a step of forming a semiconductor integrated circuit. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the first film is a nitride film, and the second, third, and fourth films are oxide films.