JPS623168U - - Google Patents
Info
- Publication number
- JPS623168U JPS623168U JP9355785U JP9355785U JPS623168U JP S623168 U JPS623168 U JP S623168U JP 9355785 U JP9355785 U JP 9355785U JP 9355785 U JP9355785 U JP 9355785U JP S623168 U JPS623168 U JP S623168U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- processing unit
- television
- radio waves
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一実施例を示すテレビジヨン
受像機の要部ブロツク図、第２図は送信側の要部
ブロツク図である。
同図中、１は本体、２は検出回路、３は演算処
理装置、４は駆動回路、５はスイツチ回路、６は
入出力部、７，８は記憶回路、９は操作装置であ
る。
FIG. 1 is a block diagram of the main parts of a television receiver showing an embodiment of the present invention, and FIG. 2 is a block diagram of the main parts of the transmitting side. In the figure, 1 is a main body, 2 is a detection circuit, 3 is an arithmetic processing unit, 4 is a drive circuit, 5 is a switch circuit, 6 is an input/output section, 7 and 8 are storage circuits, and 9 is an operating device.
Claims (1)
テレビジヨン電波を受信する受像機において、上
記テレビジヨン電波の中からコード化された信号
を検出する検出回路と、同検出回路を通して得ら
れる信号を導入し信号処理する記憶回路を含む演
算処理装置と、設定信号を与えるための操作装置
と、上記演算処理装置から得られる信号に基いて
テレビジヨン受像機の電源回路を制御するための
スイツチ回路およびその駆動回路を設けてなるこ
とを特徴とするテレビジヨン受像機。 A receiver that receives television radio waves containing pre-coded signals for each broadcast program includes a detection circuit that detects the coded signal from the television radio waves, and a signal obtained through the detection circuit. an arithmetic processing unit including a storage circuit for inputting and processing signals; an operating device for giving a setting signal; a switch circuit for controlling a power supply circuit of the television receiver based on the signal obtained from the arithmetic processing unit; A television receiver characterized by being equipped with the drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9355785U JPS623168U (en) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9355785U JPS623168U (en) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS623168U true JPS623168U (en) | 1987-01-09 |
Family
ID=30651346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9355785U Pending JPS623168U (en) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS623168U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6392177A (en) * | 1986-02-14 | 1988-04-22 | Akiyoshi Kinoshita | Program reservation system |
-
1985
- 1985-06-20 JP JP9355785U patent/JPS623168U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6392177A (en) * | 1986-02-14 | 1988-04-22 | Akiyoshi Kinoshita | Program reservation system |
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