JPS6232429U - - Google Patents
Info
- Publication number
- JPS6232429U JPS6232429U JP12378885U JP12378885U JPS6232429U JP S6232429 U JPS6232429 U JP S6232429U JP 12378885 U JP12378885 U JP 12378885U JP 12378885 U JP12378885 U JP 12378885U JP S6232429 U JPS6232429 U JP S6232429U
- Authority
- JP
- Japan
- Prior art keywords
- control device
- circuit
- alarm
- signal
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 4
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図〜第３図はこの考案の一実施例を示すも
ので、第１図は報知器の制御装置の構成を概略的
に示す図、第２図は上記構成におけるキーボード
の要部を示す図、第３図は上記動作を一般的に示
す状態遷移図であり、第４図乃至第７図は他の実
施例を示すもので、第４図はオルタネートスイツ
チを用いて構成した報知器の制御装置を概略的に
示す図、第５図は上記動作を一般的に示す状態遷
移図、第６図は１つのキースイツチによつて構成
した報知器の制御装置を概略的に示す図、第７図
は上記動作を一般的に示す状態遷移図である。
１…パーソナルコンピユータ、１０…制御装置
、１１…キーボード、１２…制御回路、１３…ブ
ザー１４…切換えスイツチ、１５…ブザー停止ス
イツチ、２０，２１…アンド回路、２２…オア回
路、３０…オルタネートスイツチ、４０…ブザー
スイツチ、３１，４１…制御回路（ＣＰＵ）。
Figures 1 to 3 show an embodiment of this invention, with Figure 1 schematically showing the configuration of the control device for the alarm, and Figure 2 showing the main parts of the keyboard in the above configuration. 3 are state transition diagrams generally showing the above operation, and FIGS. 4 to 7 show other embodiments, and FIG. 4 is a state transition diagram showing the above operation. FIG. 5 is a state transition diagram generally showing the above operation; FIG. 6 is a diagram schematically showing a control device for an alarm configured with one key switch; FIG. 7 is a diagram schematically showing a control device. The figure is a state transition diagram generally showing the above operation. DESCRIPTION OF SYMBOLS 1... Personal computer, 10... Control device, 11... Keyboard, 12... Control circuit, 13... Buzzer 14... Changeover switch, 15... Buzzer stop switch, 20, 21... AND circuit, 22... OR circuit, 30... Alternate switch, 40... Buzzer switch, 31, 41... Control circuit (CPU).
Claims (1)
じて動作される報知手段と、この報知手段を動作
可能状態あるいは動作不能状態に設定する設定手
段と、動作状態にある報知手段を停止させる停止
手段と、この停止手段の操作あるいは前記設定手
段により前記報知手段が動作可能状態に設定され
た状態において、上記制御装置本体から動作信号
が供給され、前記設定手段が動作不能状態に設定
された場合、または前記設定手段によりあらかじ
め報知手段が動作不能状態に設定された状態にお
いて、上記制御装置本体から動作信号が供給され
た場合、制御装置本体に動作停止信号を供給する
制御手段とを具備したことを特徴とする報知器の
制御装置。 (2) 前記制御手段は、設定手段により動作信号
の供給を制御し、報知手段の動作を制御する第１
のアンド回路と、設定手段により前記第１のアン
ド回路と相反して動作される第２のアンド回路と
、この第２のアンド回路の出力信号、あるいは前
記停止手段の操作に応じて前記動作停止信号を出
力するオア回路とからなることを特徴とする実用
新案登録請求の範囲第１項記載の報知器の制御装
置。 (3) 前記制御手段は、設定手段および停止手段
の操作に応じて制御されるマイクロコンピユータ
からなることを特徴とする実用新案登録請求の範
囲第１項記載の報知器の制御装置。 (4) 上記報知手段は、ブザーからなることを特
徴とする実用新案登録請求の範囲第１項記載の報
知器の制御装置。 (5) 上記報知手段は、発光表示器からなること
を特徴とする実用新案登録請求の範囲第１項記載
の報知器の制御装置。[Claims for Utility Model Registration] (1) Notifying means operated in response to an operating signal supplied from the control device main body, setting means for setting the notifying means to an operable state or an inoperable state, and an operating state. When the notifying means is set to an operable state by the operation of the stopping means or the setting means, an operation signal is supplied from the control device main body, and the setting means is activated. When the notifying means is set to an inoperable state, or when an operation signal is supplied from the control device main body in a state where the notification means is set to an inoperable state in advance by the setting means, an operation stop signal is supplied to the control device main body. What is claimed is: 1. A control device for an alarm, comprising a control means for controlling an alarm. (2) The control means controls the supply of the operation signal by the setting means, and controls the operation of the notification means.
a second AND circuit that is operated in opposition to the first AND circuit by a setting means; and a second AND circuit that stops the operation in response to an output signal of the second AND circuit or an operation of the stop means. A control device for an alarm according to claim 1, characterized in that the control device comprises an OR circuit that outputs a signal. (3) The control device for an alarm according to claim 1, wherein the control means comprises a microcomputer that is controlled according to the operations of the setting means and the stopping means. (4) The control device for an alarm according to claim 1, wherein the alarm means comprises a buzzer. (5) The control device for a notification device according to claim 1, wherein the notification means comprises a light emitting display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12378885U JPS6232429U (en) | 1985-08-12 | 1985-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12378885U JPS6232429U (en) | 1985-08-12 | 1985-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232429U true JPS6232429U (en) | 1987-02-26 |
Family
ID=31015211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12378885U Pending JPS6232429U (en) | 1985-08-12 | 1985-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232429U (en) |
-
1985
- 1985-08-12 JP JP12378885U patent/JPS6232429U/ja active Pending