JPS6232451U - - Google Patents

Info

Publication number
JPS6232451U
JPS6232451U JP1985122460U JP12246085U JPS6232451U JP S6232451 U JPS6232451 U JP S6232451U JP 1985122460 U JP1985122460 U JP 1985122460U JP 12246085 U JP12246085 U JP 12246085U JP S6232451 U JPS6232451 U JP S6232451U
Authority
JP
Japan
Prior art keywords
memory
data
external data
control circuit
holds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985122460U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985122460U priority Critical patent/JPS6232451U/ja
Publication of JPS6232451U publication Critical patent/JPS6232451U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク図である
。 ４…プログラムカウンタ、５…ＲＯＭ、６…出
力制御回路、７…入力制御回路、８…比較回路、
９…リセツト信号、１０…格納データ、１１…外
部データ。 FIG. 1 is a block diagram of one embodiment of the present invention. 4...Program counter, 5...ROM, 6...Output control circuit, 7...Input control circuit, 8...Comparison circuit,
9...Reset signal, 10...Stored data, 11...External data.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データを格納するメモルと、予め設定されたプ
ログラムにしたがつてインクリメントされるごと
に前記メモリに読出アドレスを供給するプログラ
ムカウンタと、前記メモリから読出された格納デ
ータを保持する出力制御回路と、外部から入力さ
れる外部データを保持する入力制御回路と、前記
格納データと前記外部データとを比較し一致しな
いときリセツト信号を出力する比較回路とを含む
ことを特徴とする半導体集積回路。 a memory that stores data; a program counter that supplies a read address to the memory every time it is incremented according to a preset program; an output control circuit that holds stored data read from the memory; 1. A semiconductor integrated circuit comprising: an input control circuit that holds external data input from the external data; and a comparison circuit that compares the stored data with the external data and outputs a reset signal when they do not match.
JP1985122460U 1985-08-08 1985-08-08 Pending JPS6232451U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985122460U JPS6232451U (en) 1985-08-08 1985-08-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985122460U JPS6232451U (en) 1985-08-08 1985-08-08

Publications (1)

Publication Number Publication Date
JPS6232451U true JPS6232451U (en) 1987-02-26

Family

ID=31012667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985122460U Pending JPS6232451U (en) 1985-08-08 1985-08-08

Country Status (1)

Country Link
JP (1) JPS6232451U (en)

Similar Documents

Publication Publication Date Title
JPS63150383U (en)
JPH0255341U (en)
JPS60126846U (en) Memory switching control circuit
JPH039027U (en)
JPS62169831U (en)
JPS61185127U (en)
JPH02110098U (en)
JPS6293252U (en)
JPS5871942U (en) Power control key holder
JPH0397710U (en)
JPS6427721U (en)
JPS63157899U (en)
JPS6392971U (en)
JPH022751U (en)
JPH0466646U (en)
JPS6228260U (en)
JPS6341963U (en)
JPH01155547U (en)
JPS63143953U (en)
JPH01102937U (en)
JPS60164262U (en) Transaction processing device using data card
JPS6353105U (en)
JPS6269741U (en)
JPS63126936U (en)
JPS6223336U (en)