JPS6232508B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an instruction control device for an information processing device, and particularly to a system having a buffer register for prefetching instructions and operand data. When data is updated by executing an instruction, check whether the prefetched data conflicts with the updated data and becomes old data, and if there is a conflict, write in place of the prefetched data. The present invention relates to an instruction control device that uses conflicting write data in a data register to ensure data updateability.

TECHNICAL BACKGROUND FIG. 1 is a schematic configuration diagram of a general information processing device to which the present invention is applied. In the figure, 1 is a main memory device, 2 is a main memory control device, 3 is an instruction control device, 4 is an instruction register, 5 is a read data register, 6 is a write data register, and 7 is an arithmetic execution device.

FIG. 2 shows the general form of command information used in the apparatus of FIG. In the figure, OP is the operation code, R1 is the data address of the write operand, and R2 and R3 are the data addresses of the read operand.

A plurality of instructions are prefetched into the instruction register 4 from the main memory 1 in advance. Similarly, operand data used by the instruction in the instruction register 4 during execution is prefetched into the read data register.

In operation, the instruction control device 3 sequentially takes out the instructions in the instruction register 4 and reads out the read data.
It is sent to the arithmetic execution unit 7 together with the corresponding operand data in the register 5 to execute the instruction.

By prefetching instructions and data in this way, the overhead time required to retrieve the instructions and data from main memory does not need to be taken into account during instruction execution, resulting in faster processing. .

However, the read data register that stores the prefetched data has a problem in that when the corresponding data in the main memory is updated, the consistency is lost, leading to erroneous processing. Immediately after data is written to a certain address by a write command, reading data from that same address occurs relatively frequently, so check whether the data in the read data register is updatable, that is, whether there is a conflict. There is a need for an instruction control system that can perform operations at high speed to ensure that the latest correct data is used in the event of a conflict.

Purpose and structure of the invention The purpose of the present invention is to provide an effective means for solving the above-mentioned problems.
Regarding the instructions in the instruction register, conflict
A check is made to determine what needs to be checked, and when a conflict is detected, the conflicting data in the read data register is left in the write data register rather than replaced with the correct updated data in main memory. By bypassing and using update data, efficient control is possible.

Therefore, the configuration of the present invention includes an instruction register that stores a prefetched instruction, a read data register that stores prefetched read operand data, a write data register that stores write operand data, and a write data register that stores write operand data. a conflict check flag means provided for each instruction and turned ON when there is a preceding write instruction waiting or being executed at the time of instruction prefetch; and means for holding the write operand address of the preceding write instruction. , means for detecting that the instruction to be executed is a read instruction and the conflict check flag is ON, and when the detection means detects a read instruction with the conflict check flag being ON; , means for comparing the read operand address of the amount read command and the write operand address in the holding means and outputting a conflict signal when they match; It is characterized by comprising a data select for selecting conflicting write operand data in the write data register in place of the read operand data in the read data register.

Embodiments of the Invention The present invention will be described below with reference to Examples.

FIG. 3 is a functional block diagram for explaining the basic configuration of the embodiment of the present invention. In the figure, 8 is an instruction register, which has a check flag C column for instructing a conflict check;
is a read data register, 10 is a write data register, 11 is a data selector, 12
13 is a read command R and write command W identification unit; 14 is a check flag C;
="1" (ON), 15 is a register that holds the write operand address R1 of the preceding write instruction W, 16 is a register that holds the read operand address R2/R3 of the read instruction R, and the operand address of the preceding write instruction. Conflict check unit 1 for checking conflicts with address R1
7 and 18 are AND gates, and 19 to 21 are signal lines.

The conflict check flag C of the instruction register 8 is set to ON (="1") if there is a write instruction waiting or being executed when the instruction is fetched from the main memory. When the preceding instructions are only read instructions, it remains OFF (="0"). This is because the preceding instruction is a write instruction W, and before the data write to the write operand address R1 is completed, the data at the operand addresses R2 and R3 that was prefetched in the read data register 9 is This is to indicate that the data may be old and need to be updated, and a conflict check is necessary.

To start the conflict check control operation when the outputs of the read instruction R identification unit 13 and the check flag identification unit 14 are Yes, that is, when the executed instruction is R and the check flag C is “1”. , the output of the AND gate 17 becomes "1".

On the other hand, the conflict check unit 16 checks the operand addresses R2/R3 of the execution instruction R and the R
1 register 15 is compared with the write operand address R1 of the advance write instruction W. If there is a match (conflict), a signal for switching the data selector 11 is generated by ANDing the output of the AND gate 17 in the AND gate 18.

The arithmetic execution device 12 starts executing the instruction by receiving the instruction and data. Data is,
If there is no conflict, the signal is input from the read data register 9 via the signal line 19, the upper connection of the data selector 11, and the signal line 21. However, if there is a conflict, the data selector is connected to the lower side, and the write data of the advance write command W held in the write data register 10, that is, the conflicted update data, is bypassed on the signal line 20. - Selected through routes.

In this way, all read instructions R for which the conflict check flag C is "1" are checked for conflicts, and if a conflict is detected, the data in the read data register 9 is replaced by the write data register. The corresponding latest data in 10 can be provided to the instruction execution unit as a read operand gater.

FIG. 4 is a detailed circuit diagram of the embodiment shown in FIG. 3. In the figure, 9 to 12 and 15
correspond to elements with the same reference numerals shown in FIG.

Reference numeral 21 denotes an instruction fetch control unit, which controls the operation of prefetching instructions from the main memory via the main memory controller. 22 is a decoder for detecting a write command, and 23 is a write command counter, which counts up each time a write command W is prefetched and counts down when the execution of the write command is completed, so that the wait state in the command register 8 is Or the write command W being executed
Display the number of 24 is an AND gate, which prevents other instructions from being prefetched further when the instruction fetching control unit 21 prefetches the next write instruction while the counter 23 holds the value "1". Instruction fetch control unit 2
1, a retrieval prohibition signal is given. The counter 23 always limits the number of write instructions stored in the instruction register 8 to 2 or less so that conflict checking does not become complicated.

25 is an OR gate, and as long as the counter 23 holds the value "1" or "2",
In other words, the write command W that is waiting or being executed
Conflict check flag C of the newly prefetched instruction is turned on as long as
(="1").

A decoder 26 identifies whether the executed instruction is W or R, and if it is W, stores its write operand address R1 in the R1 register. On the other hand, in the case of R, the AND gate 27 performs a logical product with the conflict check flag C, and performs control to activate the output of the conflict check circuit.

28 and 29 are conflict check circuits that compare the operand addresses R2 and R3, respectively, with the operand address R1 in the R1 register 15; 30 and 31 are AND gates that enable the output of the conflict check circuit;
2 and 33 are inverters for generating selection signals.

The data selector 11, unless a conflict signal is applied from the gates 30 to 33,
Operand data R2 and R3 of the read data register 9 are selected and supplied to the arithmetic execution unit 12. However, if a conflict is detected in either R2 or R3, the write data
The updated data in the register 10 is selected and supplied to the arithmetic execution unit 12 in place of the conflicting R2 or R3.

34 is a command transmission control section, and 35 is a write control section. When the write control section 35 finishes writing, it counts down the counter 23 and outputs a signal to the command transmission control section 34 to permit transmission of the next command.

The contents of the R1 register 15 are changed to the operand address R whenever a write instruction W is executed.
Updated with 1. Therefore, until the next write instruction is executed, the operand address R1 of the previous write instruction is used as a comparison source for conflict checking. On the other hand, the data in the write data register 10 is held until the next write command is executed, and is immediately made available if a conflict occurs in the read command in between.

Effects of the Invention As described above, according to the present invention, update control of prefetched data can be easily realized only by devising the circuit in the instruction control device, which improves the performance of the information processing device. This will make a major contribution.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a general information processing apparatus, FIG. 2 is a block diagram of instructions, FIG. 3 is a functional explanatory diagram of an embodiment, and FIG. 4 is a detailed block diagram of the embodiment. In the figure, 8 is an instruction register, 9 is a read data register, 10 is a write data register, 11 is a data selector, 12 is an arithmetic execution unit, 15 is a register that holds the operand address R1 of the write instruction, and 16 is a register that holds the operand address R1 of the write instruction. conflict·
Check circuit 17 and 18 indicate AND gates.

Claims (1)

[Claims] 1. An instruction register that stores the prefetched instruction;
A read data register stores prefetched read operand data, a write data register stores write operand data, and a write data register is provided for each instruction in the instruction register. a conflict check flag means that is turned ON when there is a preceding write instruction; a means for holding the write operand address of the preceding write instruction; and a means for holding the write operand address of the preceding write instruction; means for detecting that the flag is ON, and when the detection means detects a read instruction with the conflict check flag ON, the read operand address of the read instruction and the write in the holding means; means for comparing the operand address and outputting a conflict signal when they match; and when the conflict signal is output, replacing the read operand data in the read data register as execution data;
An instruction control device comprising: a data selector that selects conflicting write operand data in the write data register.