JPS6232544U - - Google Patents
Info
- Publication number
- JPS6232544U JPS6232544U JP12259985U JP12259985U JPS6232544U JP S6232544 U JPS6232544 U JP S6232544U JP 12259985 U JP12259985 U JP 12259985U JP 12259985 U JP12259985 U JP 12259985U JP S6232544 U JPS6232544 U JP S6232544U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- input
- electrically connected
- semiconductor package
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体パツケージの一実施例
の斜視図、第２図は第１図のＡ―Ａ線断面図、第
３図は第１図のパツケージをプリント基板に実装
した具体例の斜視図、第４図は従来の半導体パツ
ケージの一例の斜視図、第５図は第４図のＢ―Ｂ
線断面図である。
１……半導体ケース、２……外部接続端子、３
……半導体チツプ、４……ボンデイング線、５…
…試験用端子、６……プリント基板の配線パター
ン、７……プリント基板、８……導線。
Fig. 1 is a perspective view of an embodiment of the semiconductor package of the present invention, Fig. 2 is a sectional view taken along the line A--A in Fig. 1, and Fig. 3 is a specific example of the package shown in Fig. 1 mounted on a printed circuit board. FIG. 4 is a perspective view of an example of a conventional semiconductor package, and FIG.
FIG. 1...Semiconductor case, 2...External connection terminal, 3
...Semiconductor chip, 4...Bonding wire, 5...
...Test terminal, 6... Wiring pattern of printed circuit board, 7... Printed circuit board, 8... Conductor.
Claims (1)
半導体チツプの入出力端子に電気的に接続すると
ともに、プリント基板に実装されて基板のプリン
ト配線と電気的に接続される外部接続端子とを有
する半導体パツケージにおいて、前記半導体チツ
プの入出力端子に一端が接続されるとともに、前
記ケースの上面または底面から導出される試験用
端子を具備していることを特徴とする半導体パツ
ケージ。 A semiconductor package having upper and lower cases that house a semiconductor chip, and external connection terminals that are electrically connected to input/output terminals of the semiconductor chip and that are mounted on a printed circuit board and electrically connected to printed wiring on the board. 2. A semiconductor package according to claim 1, further comprising a test terminal connected at one end to an input/output terminal of the semiconductor chip and led out from the top or bottom of the case.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12259985U JPS6232544U (en) | 1985-08-12 | 1985-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12259985U JPS6232544U (en) | 1985-08-12 | 1985-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232544U true JPS6232544U (en) | 1987-02-26 |
Family
ID=31012938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12259985U Pending JPS6232544U (en) | 1985-08-12 | 1985-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232544U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112587A (en) * | 1989-09-28 | 1991-05-14 | Yamami Hosei Kk | Control device for sewing machine |
| JP2006254600A (en) * | 2005-03-10 | 2006-09-21 | Asmo Co Ltd | Circuit component |
-
1985
- 1985-08-12 JP JP12259985U patent/JPS6232544U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112587A (en) * | 1989-09-28 | 1991-05-14 | Yamami Hosei Kk | Control device for sewing machine |
| JP2006254600A (en) * | 2005-03-10 | 2006-09-21 | Asmo Co Ltd | Circuit component |
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