JPS6232620U - - Google Patents
Info
- Publication number
- JPS6232620U JPS6232620U JP12228185U JP12228185U JPS6232620U JP S6232620 U JPS6232620 U JP S6232620U JP 12228185 U JP12228185 U JP 12228185U JP 12228185 U JP12228185 U JP 12228185U JP S6232620 U JPS6232620 U JP S6232620U
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- differential amplifier
- circuit
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は信号レベル調整回路の全体回路図、第
２図は従来の信号レベル調整回路を示す回路図で
ある。
１，２……分圧抵抗、５……信号処理回路、６
……ミキシンギ回路、７……差動増幅器、８……
スイツチング回路。
FIG. 1 is an overall circuit diagram of a signal level adjustment circuit, and FIG. 2 is a circuit diagram showing a conventional signal level adjustment circuit. 1, 2... Voltage dividing resistor, 5... Signal processing circuit, 6
...Mixing circuit, 7...Differential amplifier, 8...
switching circuit.
Claims (1)
力信号の電位差を増幅出力する差動増幅器と、 この差動増幅器の一方の入力端子より入力され
る入力信号について所定の処理を行う信号処理回
路と、 この信号処理回路の出力信号と上記差動増幅器
の出力信号とをミキシングして、上記信号処理回
路の処理効果を有する信号を出力するミキシング
回路と、 上記信号処理回路の入力端に設けられ
、この信号処理回路の入力端の電位をコントロー
ル信号の印加に応じて低下させ、上記信号処理回
路への上記入力信号の入力を阻止するとともに、
上記差動増幅器の２つの入力端子の電位差を増大
させるスイツチング手段と、 を具備してなることを特徴とする信号レベル調整
回路。[Claims for Utility Model Registration] A differential amplifier that receives an input signal from two input terminals and amplifies and outputs the potential difference between the two input signals, and a specified input signal that is input from one input terminal of the differential amplifier. a mixing circuit that mixes the output signal of the signal processing circuit and the output signal of the differential amplifier to output a signal having the processing effect of the signal processing circuit; Provided at the input end of the circuit, lowering the potential at the input end of the signal processing circuit in response to application of a control signal, and blocking input of the input signal to the signal processing circuit;
A signal level adjustment circuit comprising: switching means for increasing the potential difference between two input terminals of the differential amplifier;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12228185U JPS6232620U (en) | 1985-08-09 | 1985-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12228185U JPS6232620U (en) | 1985-08-09 | 1985-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232620U true JPS6232620U (en) | 1987-02-26 |
Family
ID=31012322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12228185U Pending JPS6232620U (en) | 1985-08-09 | 1985-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232620U (en) |
-
1985
- 1985-08-09 JP JP12228185U patent/JPS6232620U/ja active Pending