JPS6232631U - - Google Patents
Info
- Publication number
- JPS6232631U JPS6232631U JP12250085U JP12250085U JPS6232631U JP S6232631 U JPS6232631 U JP S6232631U JP 12250085 U JP12250085 U JP 12250085U JP 12250085 U JP12250085 U JP 12250085U JP S6232631 U JPS6232631 U JP S6232631U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- determination result
- state determination
- sampling
- sampling data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
- Noise Elimination (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図ａ及びｂは夫々ＲＯＭに格納した記憶テ
ーブルの内容を示す図、第３図はこの考案の動作
の説明に供するタイムチヤート、第４図は従来例
を示すブロツク図、第５図は従来例の動作の説明
に供するタイムチヤートである。
図中、１はシフトレジスタ、２はクロツクパル
ス発生回路、３はＲＯＭ、４はカウンタ部、５は
立上がり微分回路、６は同期式カウンタである。
FIG. 1 is a block diagram showing an embodiment of this invention, FIGS. 2a and 2b are diagrams each showing the contents of a memory table stored in a ROM, and FIG. 3 is a time chart for explaining the operation of this invention. FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a time chart for explaining the operation of the conventional example. In the figure, 1 is a shift register, 2 is a clock pulse generation circuit, 3 is a ROM, 4 is a counter section, 5 is a rising differential circuit, and 6 is a synchronous counter.
Claims (1)
をサンプリングし、そのサンプリングデータを所
定数順次記憶するサンプリングデータ記憶部と、
該サンプリングデータ記憶部に記憶したサンプリ
ングデータと現在のパルス状態判定結果とを比較
して当該パルス状態判定結果と異なるデータ数が
所定数以上となつた時に前記入力パルス信号の状
態が変化したものと判定して前記パルス状態判定
結果を反転させる入力パルス信号状態変化監視装
置とを備えたことを特徴とするパルス信号雑音除
去装置。 a sampling data storage unit that samples the input pulse signal based on the sampling lock and sequentially stores a predetermined number of the sampled data;
Comparing the sampling data stored in the sampling data storage unit with the current pulse state determination result, when the number of data different from the pulse state determination result exceeds a predetermined number, it is determined that the state of the input pulse signal has changed. A pulse signal noise removal device comprising: an input pulse signal state change monitoring device that makes a determination and inverts the pulse state determination result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12250085U JPS6232631U (en) | 1985-08-09 | 1985-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12250085U JPS6232631U (en) | 1985-08-09 | 1985-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232631U true JPS6232631U (en) | 1987-02-26 |
Family
ID=31012744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12250085U Pending JPS6232631U (en) | 1985-08-09 | 1985-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232631U (en) |
-
1985
- 1985-08-09 JP JP12250085U patent/JPS6232631U/ja active Pending
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