JPS6233337Y2 - - Google Patents
Info
- Publication number
- JPS6233337Y2 JPS6233337Y2 JP16566386U JP16566386U JPS6233337Y2 JP S6233337 Y2 JPS6233337 Y2 JP S6233337Y2 JP 16566386 U JP16566386 U JP 16566386U JP 16566386 U JP16566386 U JP 16566386U JP S6233337 Y2 JPS6233337 Y2 JP S6233337Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- cooling plate
- resin
- adhesive layer
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001816 cooling Methods 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 27
- 239000011347 resin Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000012790 adhesive layer Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 7
- URLKBWYHVLBVBO-UHFFFAOYSA-N Para-Xylene Chemical group CC1=CC=C(C)C=C1 URLKBWYHVLBVBO-UHFFFAOYSA-N 0.000 claims description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000004132 cross linking Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 239000004809 Teflon Substances 0.000 description 5
- 229920006362 Teflon® Polymers 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000005062 Polybutadiene Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920002857 polybutadiene Polymers 0.000 description 2
- -1 polyfluoroethylene Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Description
【考案の詳細な説明】
本考案は半導体装置の実装構造に関するもので
ある。[Detailed Description of the Invention] The present invention relates to a mounting structure for a semiconductor device.
近年、ICの高速化、高集積化（大規模集積回
路LSIの開発）、半導体装置の高密度実装及び小
型化が進められてきており、このために半導体装
置の単位体積当りの発熱量が増大しており、この
熱をいかに放熱するかが課題となつている。さら
に、製品テストの際あるいは実装された後に半導
体素子に欠陥が判明してその半導体素子を交換す
る場合及びその半導体素子を積載した回路基板を
別の回路基板と交換する場合に、容易にそれぞれ
が交換できるように実装することも課題としてあ
る。 In recent years, advances have been made in increasing the speed and integration of ICs (development of large-scale integrated circuit LSI), and in increasing the density and miniaturization of semiconductor devices.As a result, the amount of heat generated per unit volume of semiconductor devices has increased. The challenge is how to dissipate this heat. Furthermore, when a defect in a semiconductor element is discovered during product testing or after it has been mounted and the semiconductor element is replaced, or when the circuit board on which the semiconductor element is mounted is replaced with another circuit board, each can be easily replaced. Another challenge is to implement it so that it can be exchanged.
これらの課題に答えるべく種々の半導体装置の
実装方法および実装構造が考案されてきた。これ
らのなかで本考案が対象とする実装構造は、第１
図の概略断面図に示したように、半導体素子
（ICチツプ）１を積載した回路基板２を冷却板３
へ装着層４を介して接着する実装構造に関連した
ものである。 In order to solve these problems, various semiconductor device mounting methods and structures have been devised. Among these, the mounting structure targeted by this invention is the first one.
As shown in the schematic cross-sectional view of the figure, a circuit board 2 on which a semiconductor element (IC chip) 1 is mounted is placed on a cooling plate 3.
This is related to a mounting structure that is bonded to the mounting layer 4 through the mounting layer 4.
上述の実装構造において、接着層にはんだ（低
融点合金）、エポキシ樹脂又は熱可塑性ポリブタ
ジエン樹脂が用いられている。この接着層の働き
は、半導体素子を積載した回路基板と冷却板とを
接着させると同時に、半導体素子に生じた熱を回
路基板から冷却板へ伝えることである。しかしな
がら、はんだを使用した場合には、はんだの熱伝
導性は良いがその融点は一般に180〜300℃であつ
て、回路基板を冷却板に取り付けあるいは外す際
にその融点まで加熱しなければならない。エポキ
シ樹脂の場合には、回路基板と冷却板との接着に
高い温度を必要としないが、架橋硬化させるとそ
の接着力が強く、外すことが困難であつて回路基
板の交換ができなくなる。実際問題として、約２
〜３mm厚さのセラミツク回路基板を外すときに割
れてしまう。 In the above-described mounting structure, solder (low melting point alloy), epoxy resin, or thermoplastic polybutadiene resin is used for the adhesive layer. The function of this adhesive layer is to adhere the circuit board on which the semiconductor elements are mounted and the cooling plate, and at the same time to transfer the heat generated in the semiconductor elements from the circuit board to the cooling plate. However, when solder is used, although the solder has good thermal conductivity, its melting point is generally 180 to 300°C, and it must be heated to that melting point when attaching or removing the circuit board from the cooling plate. In the case of epoxy resin, high temperatures are not required for adhesion between the circuit board and the cooling plate, but once it is crosslinked and cured, its adhesive strength is strong and it is difficult to remove, making it impossible to replace the circuit board. As a practical matter, about 2
~3mm thick ceramic circuit board breaks when removed.
本考案の目的は、従来方法よりも回路基板の冷
却板への着脱が容易な半導体装置の実装構造を提
供することである。また、従来方法での欠点を解
消した実装方法を提供することも本考案の目的で
ある。 An object of the present invention is to provide a mounting structure for a semiconductor device in which mounting and removing a circuit board on a cooling plate is easier than in the conventional method. Another object of the present invention is to provide a mounting method that eliminates the drawbacks of conventional methods.
上述の目的が、半導体素子を搭載したセラミツ
ク回路基板と、冷却板と、該セラミツク回路基板
と該冷却板との間にはさまれた架橋硬化により強
い接着力を呈する厚さ50〜300μｍのシート状樹
脂接着層と、該セラミツク回路基板もしくは該冷
却板の少なくとも一方の該樹脂接着層と接する面
側に形成されかつ該樹脂接着層との接着力を著し
く低下せしめる厚さ0.05〜10μｍのパラキシレン
樹脂薄膜又は含弗素樹脂コーテイング膜と、該樹
脂接着層をはさんだ回路基板と冷却板とを加圧固
定する着脱機構とを有することを特徴とする半導
体装置の実装構造によつて達成される。 The above purpose is to provide a ceramic circuit board on which a semiconductor element is mounted, a cooling plate, and a 50-300 μm thick sheet sandwiched between the ceramic circuit board and the cooling plate and exhibiting strong adhesive strength due to crosslinking and curing. paraxylene with a thickness of 0.05 to 10 μm, which is formed on the side of at least one of the ceramic circuit board or the cooling plate that is in contact with the resin adhesive layer, and which significantly reduces the adhesive force with the resin adhesive layer. This is achieved by a semiconductor device mounting structure characterized by having a thin resin film or a fluorine-containing resin coating film, and an attachment/detachment mechanism for pressurizing and fixing a circuit board sandwiching the resin adhesive layer and a cooling plate.
前述の樹脂接着層はシート状の樹脂が好まし
く、その厚さは50ないし300μｍが適当である。
50μｍ以下の厚さでは回路基板及び冷却板にうね
り（平行性の悪さ）があつた場合に、回路基板と
冷却板との間に空気が存在して熱伝導性が低下す
る可能性がある。また、300μｍ以上の厚さの樹
脂層では、樹脂自身の熱伝導率は４〜８×
10-4cal／cmｓ℃であるので熱伝導がはんだに比
べ低く好ましくない。そして、この樹脂の熱伝導
を高めるために金属粉又は酸化物粉体を樹脂に混
合することもできる。なお、樹脂としてポリブタ
ジエン樹脂、エポキシ樹脂、シリコーン樹脂が使
用できる。 The resin adhesive layer mentioned above is preferably a sheet-like resin, and its thickness is suitably 50 to 300 μm.
If the thickness is less than 50 μm, if the circuit board and cooling plate are undulated (poor parallelism), air may exist between the circuit board and the cooling plate, resulting in a decrease in thermal conductivity. In addition, in a resin layer with a thickness of 300 μm or more, the thermal conductivity of the resin itself is 4 to 8 ×
10 -4 cal/cms°C, which is undesirable because its thermal conductivity is lower than that of solder. In order to enhance the thermal conductivity of this resin, metal powder or oxide powder can also be mixed with the resin. Note that polybutadiene resin, epoxy resin, and silicone resin can be used as the resin.
回路基板及び／又は冷却板の樹脂接着層をはさ
む面に付着させる皮膜としてパラキシレン樹脂薄
膜（U.C.C社商品パリレンの薄膜）又は含弗素樹
脂（ポリ弗化エチレンで商品名テフロン）のコー
テイング膜を使用することが好ましい。この皮膜
によつて樹脂接着層の回路基板と冷却板との接着
力が著しく低下するために回路基板を容易に外す
ことが可能になる。この皮膜は多少のピンホール
があつても薄いほうがよく0.05〜10μｍの厚さが
適切である。接着力が著しく低下しているので外
力が回路基板にかかると外れやすく、これを防止
するために着脱機構、例えば、ボルト又はクラン
プを利用して回路基板を冷却板に固定する。前述
の皮膜を回路基板と冷却板の両方に付着させても
よく、またはどちらか一方のみに付着させてもよ
い。 A paraxylene resin thin film (UCC product Parylene thin film) or a fluorine-containing resin coating film (polyfluoroethylene, trade name Teflon) is used as a film to be attached to the surface of the circuit board and/or cooling plate that sandwiches the resin adhesive layer. It is preferable to do so. This film significantly reduces the adhesive strength of the resin adhesive layer between the circuit board and the cooling plate, making it possible to easily remove the circuit board. Even if this film has some pinholes, it is better to be thin, and a thickness of 0.05 to 10 μm is appropriate. Since the adhesive strength is significantly reduced, the circuit board is likely to come off when external force is applied to the circuit board. To prevent this, the circuit board is fixed to the cooling plate using an attachment/detachment mechanism, such as a bolt or a clamp. The coating described above may be applied to both the circuit board and the cooling plate, or only to either one.
冷却板は放熱板であり、その材質は銅、銅合
金、アルミニウムあるいはアルミニウム合金が望
ましい。また、その他伝導性の良い金属板を使用
することができる。 The cooling plate is a heat sink, and its material is preferably copper, copper alloy, aluminum, or aluminum alloy. Also, other metal plates with good conductivity can be used.
本考案に係る半導体装置の実装構造を第２図の
概略断面図に示した実装された半導体装置に関連
して説明する。 The mounting structure of a semiconductor device according to the present invention will be explained in relation to the mounted semiconductor device shown in the schematic cross-sectional view of FIG.
半導体素子（ICチツプ）１を積載した回路基
板（セラミツク製回路基板）２及び冷却板３にボ
ルトのための孔７を設けておく。回路基板２及び
冷却板の表面に厚さ0.05ないし10μｍのテフロン
コーテイング膜５及び６を塗布する。次に、厚さ
50ないし300μｍのシート状樹脂接着層４をテフ
ロンコーテイング膜５及び６に接触するように回
路基板２と冷却板３とではさむ。そして、ボルト
孔７にボルトを挿入して回路基板２と冷却板３と
を軽く圧力をかけるように固定する。 Holes 7 for bolts are provided in a circuit board (ceramic circuit board) 2 on which a semiconductor element (IC chip) 1 is mounted and a cooling plate 3. Teflon coating films 5 and 6 with a thickness of 0.05 to 10 μm are applied to the surfaces of the circuit board 2 and the cooling plate. Next, the thickness
A sheet-like resin adhesive layer 4 having a thickness of 50 to 300 μm is sandwiched between the circuit board 2 and the cooling plate 3 so as to be in contact with the Teflon coating films 5 and 6. Then, bolts are inserted into the bolt holes 7 and the circuit board 2 and the cooling plate 3 are fixed by applying light pressure.
上述の態様ではポリ弗化エチレン（テフロン）
コーテイング膜を回路基板と冷却板との両方に塗
布するが、これらのうち一方のみに塗布しただけ
でもよい。 In the above embodiment, polyfluoroethylene (Teflon)
Although the coating film is applied to both the circuit board and the cooling plate, it is also possible to apply the coating film to only one of them.
したがつて、本考案に係る半導体装置の実装構
造によつて、回路基板から冷却板への放熱は従来
構造と同じであるが、回路基板及び／又は冷却板
との樹脂層の接着力を著しく下げてあるので、回
路基板の冷却板からの取り外しが容易になる。す
なわち、従来のように所定温度まで加熱すること
なくボルトを外すという簡単な作業の後に容易に
取り外すことができる。 Therefore, with the mounting structure of the semiconductor device according to the present invention, heat radiation from the circuit board to the cooling plate is the same as in the conventional structure, but the adhesive force of the resin layer with the circuit board and/or cooling plate is significantly improved. The lowered position facilitates removal of the circuit board from the cooling plate. That is, it can be easily removed after a simple operation of removing the bolt without heating it to a predetermined temperature as in the conventional case.
第１図は従来方法によつて実装された半導体装
置の概略断面図であり、及び、第２図は本考案の
構造によつて実装された半導体装置の概略断面図
である。
１……半導体素子、２……回路基板、３……冷
却板、４……樹脂接着層、５，６……皮膜（テフ
ロンコーテイング膜）、７……ボルト孔。
FIG. 1 is a schematic sectional view of a semiconductor device mounted by a conventional method, and FIG. 2 is a schematic sectional view of a semiconductor device mounted by the structure of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Circuit board, 3... Cooling plate, 4... Resin adhesive layer, 5, 6... Film (Teflon coating film), 7... Bolt hole.
Claims (1)
冷却板と、該セラミツク回路基板と該冷却板との
間にはさまれた架橋硬化により強い接着力を呈す
る厚さ50〜300μｍのシート状樹脂接着層と、前
記セラミツク回路基板もしくは前記冷却板の少な
くとも一方の該樹脂接着層と接する面側に形成さ
れかつ該樹脂接着層との接着力を著しく低下せし
める厚さ0.05〜10μｍのパラキシレン樹脂薄膜又
は含弗素樹脂コーテイング膜と、前記樹脂接着層
をはさんだ前記回路基板と前記冷却板とを加圧固
定する着脱機構とを有することを特徴とする半導
体装置の実装構造。 A ceramic rotating substrate with semiconductor elements mounted on it,
a cooling plate, a sheet-like resin adhesive layer with a thickness of 50 to 300 μm that exhibits strong adhesive strength due to crosslinking and curing, which is sandwiched between the ceramic circuit board and the cooling plate; A paraxylene resin thin film or a fluorine-containing resin coating film with a thickness of 0.05 to 10 μm, which is formed on the side in contact with at least one of the resin adhesive layers and which significantly reduces the adhesive force with the resin adhesive layer, and the resin adhesive layer. A mounting structure for a semiconductor device, comprising an attachment/detachment mechanism for pressurizing and fixing the circuit board and the cooling plate sandwiched therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16566386U JPS6233337Y2 (en) | 1986-10-30 | 1986-10-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16566386U JPS6233337Y2 (en) | 1986-10-30 | 1986-10-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276541U JPS6276541U (en) | 1987-05-16 |
| JPS6233337Y2 true JPS6233337Y2 (en) | 1987-08-26 |
Family
ID=31095902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16566386U Expired JPS6233337Y2 (en) | 1986-10-30 | 1986-10-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6233337Y2 (en) |
-
1986
- 1986-10-30 JP JP16566386U patent/JPS6233337Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6276541U (en) | 1987-05-16 |
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