JPS6234415A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate an optional kind of pulse signal with an optional period synchronized with a basic clock by varying the preset value of a counter successively with the output of a shift register. CONSTITUTION:Presettable counters 22-25 count up with an input SCLOCK and the output CAR of the counter 25 becomes 'H' when a counted value reaches a preset value. A 4-bit shift register 26 shifts data in the order of A B C D every time an input CK is supplied. The input to the shift register 26 becomes 'H' because of a gate 21 when outputs A, B, and C of the shift register 26 are 'L', so the output A is 'H' when an output D is 'H'. Preset inputs '0'-'3' to the counters 22-25 are preset with the outputs A-D of the shift register 26. A fixed 'L', a fixed 'H', the outputs 'A' and 'B' of the shift register 26, and the OR output 'AVD' between the 'A' and 'D' are connected to preset terminals of the counters 22-25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse generation circuit for a computer or the like.

[Background of the invention]

FIG. 4 shows a conventional example.

41 to 44 are counters. Counter 41 is a hexadecimal counter and is 8! ! Counter 4 at a cycle of 16T in Figure 1
The C output of 1 becomes rHJ, and the flip-flop 46 is set in the counter 42 and J-. The counter 42 is an octal counter, and the C output of the counter 42 becomes "H" at a cycle of 8T, setting the flip-flop 47 in the run 443 and J-, and resetting the flip-flop 46 in J-. Therefore, the output B of the flip-flop 46 is applied to J-.
has a period of 8T, as shown in FIG. counter 4
3 is an 8192 binary counter, and the counter 44 is 51
It is a binary counter.

45 to 48 are flip-flops for J-, and the rcJ outputs of all counters 41 to 44 are rJJ rKJ inputs, so the A, C, and D outputs are also set in the same way.
According to this method, the output according to the time of 1,000 yards of the first step is obtained, 41 is ICI, 42 is ICI, 4
3 has 4 ICs, 44 has 3 ICs, 45 to 48 has 2 ICs, and other gates have 2 ICs, for a total of 12 ICs.

[Purpose of the invention]

An object of the present invention is to provide a pulse generation circuit which can be realized with a small number of ICs, and which can realize a decrease in the number of required pulses and an increase in ICd compared to the conventional example.

[Summary of the invention]

Conventionally, the number of counters or decoders is increased by the number of required pulse types, and the number of ICs is large. This example is based on the concept of using one type of counter and sharing the counter by changing the preset value 19 times. The present invention uses a logic circuit consisting of a counter and a shift register to sequentially change the preset value of the counter using the output of the shift register, thereby generating a pulse signal of any type and any period synchronized with a basic clock. It is characterized by this.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

The device requires a pulse signal synchronized with a basic clock. As an example, FIG. 1 shows a pulse signal necessary for a CCD sensor and an analog circuit used in OCR, FAX, etc. 5CLOCK is a basic clock and is continuously output at a period of T. In this example, it corresponds to 1 bit of the CCD sensor.

Pulse signal A is a signal that activates the CCD sensor, and pulse signal B is a pulse signal that inhibits rising overshading of the video circuit. Pulse signal c42
．． This signal has a period of "l(") for shifting the ccD sensor, and is 8.192 bits in this example.The pulse signal is a pulse signal for the blanking time during which no signal is taken out from the CCD sensor.

In this example, commonly used A = 16T, B =
This will be explained using the values of 8T, C20, 192T, and D=s12T, but these values can be arbitrarily varied.

In FIG. 2, 22 to 25 are presettable counters, which count up by inputting 5CLOCK, and when the count value becomes the same as the preset value, it becomes the CAR output HJ of the counter 25.

26 is a 4-bit shift register, which shifts data from A-+B-*C-+D every time a large CK input is received. The input to the shift register 26 is provided by the gate 21.

When the A, B, and C outputs of the shift register 26 are "L", "
Therefore, as shown in FIG. 1, the D output becomes rHJ, and then the human output becomes rHJ.

The preset inputs "0-3" of the counters 22-25 are preset by the outputs A-D of the shift register 26 according to FIG.

rLJ fixed, rHJ fixed, and r of shift register 26
Aj output, "B" output, and rAJ and [DJ's 0Ra
The AVDJ is connected to the presets of the counters 22 to 25. Therefore, as shown in FIG. 3, the presets corresponding to the count values are input, and the cycles of the outputs A and D of the shift register 26 are determined. Ru.

In FIG. 1, the output A of the shift register 26 is rHJ
Consider the state of In this state, A=“HJ and B~D−
“Since it is LJ, the preset conditions in Figure 3 are (FFF8
)16, and the output B of the shift register 26 is set, and at the same time, the counters 21 to 25 have (FFF8)t.
It is preset as s. Thereafter, the counters 22 to 25 become (FFFF) 16 at a cycle of 8T, the carry output HCAR signal of the counter 25 is output, and the shift register 26
The output B of is reset, the output C is set, and the counter 2
Set the next preset value (EOOO)la to 2 to 25.

Set the following in the same way.

According to this embodiment, as shown in FIG.
5 tickets, 1 at other gates. This can be realized with a total of 6 ICs, which has the effect of reducing the number of ICs.

[Effects of the Invention] According to the trap of the present invention, the number of ICs can be reduced, and even if the number of pulse types increases, the increase in the number of ICs is small compared to the nine conventional examples.

[Brief explanation of the drawing]

FIG. 1 is a time chart of an embodiment of the present invention, FIG. 2 is a block diagram of this embodiment, FIG. 3 is a counter preset diagram, and FIG. 4 is a block diagram of a conventional example. 21...AND gate 2°2~25...Counter 26...Shift register 41~44...Counter 1. -0, 2nd Roro (4th B)

Claims (1)

[Claims] 1. In a logic circuit consisting of a counter and a shift register, by sequentially changing the preset value of the counter using the output of the shift register, it is possible to generate any type of pulse signal with any period synchronized with the basic clock. Characteristic pulse generation circuit.