JPS6235734A - Loop integrated communication system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information exchange bus within a station device in a high-speed loop communication system, and particularly relates to a bit/byte/bit/byte/information exchange bus.
The present invention relates to a loop integrated communication system suitable for an integrated network in which information is transmitted by occupying loops in various units such as time slot corners.

[Background of the invention]

Conventionally, loop communication systems have been widely used in fields such as wide-area production management and calculation control in electric power, steel, and chemical plants, as seen in data technology. Recently, it has also been used to connect computers, facsimiles, telephones, etc. in offices.

On the other hand, in recent years, due to the rapid progress of optical fiber transmission technology, high-speed loop communication of about 100 Mbit/s7 has become possible.
It is becoming possible to construct a computer system, and along with this, loop communication systems can be used not only for computer-related data, but also for computer-related data.
Disparate information with different transmission speeds, such as images and audio information,
There is an opportunity to build an integrated network that integrates and transmits different exchange systems.

One of these rauna loop communication systems is 1. For example, Shuhata, Sano, Hakiki, "100 Mbit/s ring-type optical local network connecting path-type networks," Nikkei Electronics J, December 5, 1983, issue 1. ) p1
73-199.

Here, a case is shown in which information is exchanged between the information device and the loop via a common path, but information is exchanged in units of time slots, at a single transmission rate, and in packets. Only exchange is possible.

Therefore, it is not intended for diverse information transmission from various 1# information terminals as an integrated network.

[Purpose of the invention]

An object of the present invention is to provide an information exchange path method within a station device that enables information transmission by occupying the loop in various units such as bits/bytes/time slots in a high-speed loop communication system. be.

[Summary of the invention]

The present invention provides each station with a transmission frame demultiplexing circuit, a plurality of information device connection adapters, and an information exchange path for interconnecting these, and performs loop occupation/release/data transfer on the information exchange path. It is an information exchange bus characterized by allowing transmission/reception to be performed.

Another feature is that the information exchange bus is provided with a byte sending signal line and a bit sending signal line, making it possible to send/receive information in units of any number of bits.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail according to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a loop communication system to which the present invention is applied. In Fig. 1, l is a loop transmission line such as an optical fiber, 2 is a reference clock generation,
This is a loop management station <LET) that generates time slots and monitors and controls the entire loop. In addition, 3 (3-1 to 3-4) is a data transmission/reception station device (8T1 to ST4), which includes a packet switching information device 5PT (for example, a computer, a workstation, etc.), a line switching information device CT (talk to, fax,
FIG. 2 is an explanatory diagram of an example of a frame structure on a loop transmission line 1 showing a second embodiment of the present invention. F is frame, TS (
TaO2-TS#m) is a time slot, and F8 is a frame synchronization signal, which is a signal for identifying the delimiter of the following time slots) TS. On the loop transmission line 1 in Fig. 1, 7 frames of this length are arranged so that they circulate without any break.
The loop management station 2 corrects the circuit delay time.

Each time slot for packet switching and circuit switching consists of a fixed length, and the packet/time M'lZ exchange bit P/C (
P/C = 12 packet switching, P/C = 0 indicates circuit switching). Note that the CTL field is provided with an F/B bit indicating whether the time slot is empty or occupied. Note that the F/B bit is used only when exchanging packets.

In addition to the CTL field, the packet switching time slot includes a destination station address DA, a source station address SA, and a data length field LNG indicating the effective information length within the time slot. The information field DATA is a field for transmitting information from the information device. In packet switching, an arbitrary number of these time slots are occupied to transmit packets of arbitrary length.
It is something that can be done.

In the circuit-switched time slot, the information field is divided into a plurality of channels CH as in the illustrated example, and one or more channels are assigned to each device to achieve transparent transmission. The free/occupied bit F/B indicates whether each channel is free or occupied. Note that although the channel is illustrated as being composed of 8 bits, it goes without saying that it can be composed of arbitrary bits.

FIG. 3 is a block diagram showing an example of the configuration of the data sending/receiving station 3 according to an embodiment of the present invention. In FIG. 3, a data transmission/reception station 3 receives data from a loop transmission path 1 via a receiver 10, extracts a clock from the received data string, and reproduces the data.

20 is a transmitter that sends data in Babbitt/real on a transmission path. 30 is a time slot multiplexing/separating circuit;
It has a function of identifying the frame structure shown in FIG. 2, breaking down time slots into, for example, 8-bit units and sending them to the reception bus, or assembling 8-bit unit information on the transmission bus into time slots.

Reference numeral 40 denotes an information exchange bus for reception and transmission, through which, for example, information in units of 8 bits, timing signals, etc. are periodically transferred. Reference numeral 60 denotes an information device connection adapter, which controls an interface for devices.

Controls packet switching/circuit switching, etc.

In the present invention, in the configuration shown in FIG. 3, all information of the time slots on the transmission line l is sent onto the reception bus 40-1, and the information device connection adapters 60 each judge this information,
Information is exchanged with the loop transmission line (loop occupancy, data transmission/reception) by selecting information on the transmission bus 40-2 as necessary.

FIG. 4 is a block diagram showing one embodiment of the time slot multiplexing/separating circuit 30. 301 is a clock generator that extracts a clock from data received by the receiver 10; 302;
is the frame synchronization signal F in the frame configuration shown in FIG.
Frame synchronization is detected based on S. 303 is
The time slot separation circuit identifies the time slot based on the frame synchronization signal, specifically, supplies the time slot synchronization signal b-2 and the data transfer timing b-3 on the reception bus. 305 is a circuit for serial/parallel conversion, and 311 is a circuit for parallel/serial conversion. 306,307°308
rt, is a buffer register for parallel data.

304 is a flip hoop for delaying the frame synchronization signal by the upper data transfer timing, and 313 is a frame synchronization signal generation circuit. 309 is an exclusive OR circuit, and 310 and 312 are selectors for selecting data to be output. Further, b-4 is the data transfer typing of the transmission bus, which may basically be the same as that of the reception bus and b-3.

FIG. 5 shows the timing of each signal on the transmitting/receiving bus 40 using FIG. 4 and FIG.
The operation of the separation circuit 30 will be explained. The data parallelized by the serial/parallel conversion circuit is always stored in the buffer register 30.
6,307. Selector 310 parallel-serial conversion circuit 311
．． The path of the selector 312 forms a loop, and the output of the buffer register 306 is output at various timings (b
-1 to b-3) are output to the reception bus 40-1. By determining the data on this reception bus, each information device connection adapter 60 learns the trigger for starting the data reception operation and transmission operation. The receiving operation of bucket conversion is
As shown in the frame structure in Figure 2, because the destination station address DA is the own station address, the receiving operation for line quality switching uses a channel predetermined by connection control between information devices. This is done by identifying.

The trigger for starting the transmission operation is an empty/occupied pit in the control field CTL for packet switching, and an empty/occupied pit for circuit switching.
This is done by determining the occupancy (F/B) field.

The data to be transmitted is selected from the following three types by the selector 310 and sent.

(1) Send received data as is (output of buffer register 307) (2) Send data on the transmission bus as is (output of buffer register 308) G) Exclusive OR of received data and data on the transmission bus Send data. In this transmission mode, the information device connection adapter can transmit information bit by bit to the vacant/occupied field of the circuit switching time slot shown in FIG.

In order to select these three types of transmission modes, the information equipment connection adapter 60 connects the byte transmission signal line b-5 (selects the mode (2) above) and the bit transmission signal line b-6 (selects the mode (3) above). (selection).

FIG. 5 shows the case of transmission mode (2), in which the empty state of the control field CTL is determined based on the time slot synchronization signal TS-8YNK on the reception bus.

This shows a case where data below the control field is sent onto the transmission bus with a one-transfer timing delay.

Next, the transmission and reception operations performed by the information device connection adapter 60 using the information exchange bus will be described.

FIG. 6 shows an embodiment of an adapter for connecting information equipment that performs circuit switching. FIG. 7 is a flowchart illustrating the operation of the adapter configured in FIG. 6.

Reference numeral 601 denotes a line switching control unit, which has a built-in microcomputer, for example, and controls the entire adapter. 602 is an interface circuit with information equipment. 603 is
It is used by the packet transmission/reception control unit to request a connection and inform the other party of the time slot number and channel number to be used.

Reference numeral 604 denotes an F/B field control unit that sends data bit by bit to the F/B field of the circuit switching time slot shown in FIG.

6°05 is a data transmitting/receiving buffer, which is a backup memory for transmitting and receiving data to a designated time slot number and channel number.

606 is a time slot control unit which outputs a frame synchronization signal FS (b-1) and a time slot synchronization signal TS 5Y.
The operation timing of each part is generated based on the data transfer timing (b-3) and the data transfer timing (b-3).

Next, the operation of the information equipment adapter will be explained using the flowcharts shown in FIGS. 7 to 11. When the line switching control unit 601 receives a connection request from an information device, it instructs the F/B field control unit 604 to occupy a channel (A1).
. Upon receiving the time slot synchronization signal TSSYN, the F/B field control unit 604 determines that the time slot is for line switching (B1), checks the F/B field (B2), and determines if there is an empty channel. sends out the bit sending signal b-6.

Only the relevant bit is sent as "l" (B3).

When this operation is completed, the F/B field control unit 604
notifies the circuit switching control unit 601 of channel occupation completion, time slot number, and channel number (A3
). Next, send a connection request and time slot number to the information terminal adapter of the connection partner.

In order to notify the channel number, the packet transmission/reception control unit 603 is instructed to transmit a packet (A4). The packet transmission/reception control unit 603 determines whether the time slot is for circuit switching or packet switching, and also confirms the F/B pit width C1>.

The packet information is then sent (C2). If all the packet information cannot be sent in one time slot, the above operation is further repeated (C3).

When this transmission operation is completed, the packet transmission/reception control unit 6
03 begins the operation of receiving a response packet to the connection request (A6). In the reception operation, the P/C bit = 1 and F'/B = 1 of the time slot control field CTL are determined (DI), and according to this condition, υdestination station address DA is
If it is the own station address (B2), the packet information is received (B3).

1 if the packet information spans multiple time slots
will have the reception of the next timeslot synchronization signal (
B4). Upon receiving the response to the connection request, the circuit switching control unit 601 instructs the data transmission/reception buffer to start transmitting/receiving data (A7). The data transmission operation starts upon reception of a frame synchronization signal, resets the T8 counter (El), and increments the TS counter each time a time slot synchronization signal is received (B2). By detecting the specified time slot number (B3) and channel number (E4), data is sent to the channel (E5
). This data transmission operation is repeated until a disconnection request is generated from the information device (A9), and upon generation of the disconnection request, the disconnection process is executed and the communication is terminated.

(AIO).

[Effects of the Invention] According to the present invention, it is possible to transmit information by occupying a loop transmission path in various units of bits/bytes/time slots via an information exchange bus. This has the effect of accommodating a variety of different information devices such as.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example configuration of a loop communication system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a frame configuration side of an embodiment of the present invention, and FIG. 3 is a data transmission and FIG. 4 is a block diagram of a detailed configuration example of a time slot multiplexing/demultiplexing circuit according to an embodiment of the present invention, FIG. 5 is an operation timing chart of the transmission/reception bus, and FIG. FIGS. 7 to 11, a block diagram of an example configuration of an information device connection adapter according to an embodiment of the present invention, are flowcharts for explaining the operation of the information device connection adapter. l... Loop transmission jL 2... Roof management station, 3... Data transmission/reception station, 10.
...Receiver, 20...Transmitter, 30...Time slot multiplexing/demultiplexing circuit, 40...Transmission/reception information conversion bus, 60...Information equipment connection adapter.

Claims (1)

[Claims] 1. In a loop communication system consisting of a plurality of information devices, a plurality of stations accommodating these devices and transmitting information, and a transmission line connecting the stations, each station has a transmission line. A frame multiplexing/demultiplexing circuit, a plurality of information device connection adapters, and an information exchange bus interconnecting the multiplexing/demultiplexing circuit and the plurality of information device connection adapters are provided, one frame is composed of a plurality of time slots, and each time slot is A time slot control field is provided in the circuit switching time slot to indicate whether the time slot is for packet switching or circuit switching, and whether the time slot is vacant or occupied. A channel control field is provided for each channel to indicate whether the channel is free or occupied, and each station transmits information on the information exchange bus according to the contents of the time slot control field and channel control field. A loop integrated communication system characterized by occupying/opening a line and transmitting/receiving data. 2. The loop integrated communication system according to claim 1, wherein the number of channels accommodated in a circuit switching time slot is set in advance, and the bit length is determined for each channel. 3. In claim 1, the information exchange bus includes:
A byte sending signal line and a bit sending signal line are provided, and the information device connection adapter controls the demultiplexing circuit using the byte sending signal line and the bit sending signal line, and loops such that information is sent/received in units of arbitrary bit numbers. Integrated communication system.