JPS623590B2 - - Google Patents
Info
- Publication number
- JPS623590B2 JPS623590B2 JP54010772A JP1077279A JPS623590B2 JP S623590 B2 JPS623590 B2 JP S623590B2 JP 54010772 A JP54010772 A JP 54010772A JP 1077279 A JP1077279 A JP 1077279A JP S623590 B2 JPS623590 B2 JP S623590B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- glass
- layer
- pellet
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
本発明は半導体装置、特にDHDガラス封止ダ
イオードの電極構造に関する。
一般に、DHDガラス封止ダイオードは、半導
体素子〔以下単にペレツトと称する〕の両表面を
ヒートシンクとなる電極リードによつて挾み込む
構造を特徴としている。
この場合、ペレツトは、その表面にバンプと称
される突起状の電極が造られ、裏面には接触抵抗
を低くするため適当な鑞材層が形成されており、
これらのバンプ及び鑞材層面に電極リードを接続
するようにしている。
ところでペレツト裏面に対する鑞材としては、
従来一般に金あるいは金を主体とする合金が用い
られ、次いでこの全面に銀層をメツキにより形成
した後、ペレツトをデユメツト線からなる電極リ
ード間に挾み込み、その周面をガラス管により封
止して組み立てられている。
しかしながら、このように形成されたペレツト
は、ガラス管で封止する際の加熱処理によつて、
金、シリコン、銀、銅等からなる好ましくない合
金が形成されるため電気的特性の点で接触抵抗が
大きくなり、コンタクト不良を発生していた。
又、DHDガラス封止ダイオードは上述のよう
に、ペレツトの両電極を電極リード線で挾み込み
ガラス封止する構造であるから、両電極の電気的
接続は銀バンプ電極をクツシヨン材とした機械的
接続となるため、温度サイクル試験や加熱試験等
の熱的環境雰囲気に対してルーズコンタクトの原
因となる欠点を含んでいた。
本発明はかゝる欠点を除去するためになされた
もので、ペレツト裏面の鑞材が剥れたり、ガラス
封止の後のルーズコンタクトのない電極構造を得
ることにある。
本発明の要旨とするところは、一主面に銀バン
プ電極が形成されたシリコン基板の他主面にCr
の薄層を被着し、Si，Crの強固な接着層を形成
する。更にNi，Agの薄層を逐次被着形成して熱
応力に優れた電極構造を形成する。次にこのよう
に形成した電極構造のSiペレツトの両電極間を
Cu材等からなる電極リードで挾んでガラス封止
する事により、前記Siペレツトの一方に於いて、
柔軟性の銀バンプ電極を電極リードに弾接させ
る。又他方裏面側に於いて、シリコン基板に対し
て熱膨張係数が順次大きく形成されたCr，Ni，
Agの積層電極を他方の電極リードに弾接させ
る。
このように、本発明で得られるDHDガラス封
止ダイオードは、熱応力に優れた弾力性の両電極
で電極リードに当接せしめ、ガラス封止する際の
加熱処理やガラス封止後の熱的環境雰囲気に対し
てもルーズコンタクトの発生しない良好な電極構
造が得られる。
以下本発明の実施例を図面を参照しつつ詳述す
る。
第１図に於て、１はＮ形シリコン基板であり、
拡散処理によりＰ形導電層２を形成し、このＰ形
導電層２に対しバンプ電極３を形成する。４は基
板１表面を覆う絶縁保護膜、例えばSiO2であ
る。シリコン基板１の下面にはCr，Ni，Agの薄
膜層５，６，７が逐次蒸着法により被着されて、
積層電極８が形成される。このシリコン基板１の
下面は上記薄膜層の被着前にエツチング法又はサ
ンドブラスト法により表面をあらし接着強度を高
めるようにしている。
かかる構造に形成されたシリコン基板１は１個
の素子毎に分離され、ペレツト１０が形成され
る。このペレツト１０は第２図に示すように２個
の電極リード１１，１２により両主表面から挾み
込むようにし、且つペレツト１０がガラス管１３
で包囲されるようにして図示しないが、電極リー
ド１１の上端より重鍾で加圧しながら約650℃で
加熱し、ガラス管１３を溶融せしめてペレツト１
０が封着される。こゝで電極リード１１，１２と
しては、一般にFe−Ni芯線Cu被覆したジユメツ
ト線が用いられ、これらのリード１１，１２は一
般にガラス管内にある電極導体部１４と外部に出
ているリード部１５とは違つた経に形成され、電
極取り出しと封止に適合するよう考慮されてい
る。
本発明は以上のように構成されており、シリコ
ン基板のSiと被着されるCrの強固な密着が得ら
れる。こゝでCrは高融点金属であり、従来の如
くガラス封止する際の加熱処理によつてAu−Si
−MgやAu−Si−Ag−Cu等の多元合金を形成し
て接触抵抗を大きくしたり、コンタクト不良を発
生することがなくなる。又、こゝで特に注目すべ
き点は、シリコン基板に被膜され電極リードに当
接されるCr−Ni−Ag層は、その被膜金属の線膨
張係数が夫々0.84×10-5cm／cm・deg、1.33×10-5
cm／cm・deg、１・97×10-5cm／cm・degと逐次
大きくした金属膜が被覆され熱応力に優れた薄膜
の積層電極を形成したから、ガラス封止の熱処理
や封止後の熱サイクル試験、加熱試験等の熱的環
境雰囲気に対しても、熱疲労を生じて劣化した
り、ルーズコンタクト等の不良を生ずることが解
消される。
尚、本発明で得られたダイオードＡと従来のダ
イオードＢとの比較試験結果を第１表に示す。
The present invention relates to a semiconductor device, particularly to an electrode structure of a DHD glass-sealed diode. In general, a DHD glass-sealed diode is characterized by a structure in which both surfaces of a semiconductor element (hereinafter simply referred to as pellet) are sandwiched between electrode leads that serve as a heat sink. In this case, a protruding electrode called a bump is formed on the surface of the pellet, and a suitable solder layer is formed on the back surface to reduce contact resistance.
Electrode leads are connected to these bumps and the solder layer surface. By the way, as a solder material for the back side of pellets,
Conventionally, gold or a gold-based alloy was generally used, and then a silver layer was formed on the entire surface by plating, and then the pellet was inserted between electrode leads made of dumet wire, and the surrounding surface was sealed with a glass tube. It has been assembled. However, the pellets formed in this way are heated during sealing in a glass tube.
Since an undesirable alloy consisting of gold, silicon, silver, copper, etc. is formed, contact resistance increases in terms of electrical characteristics, resulting in contact failure. In addition, as mentioned above, the DHD glass-sealed diode has a structure in which both electrodes of the pellet are sandwiched between electrode lead wires and sealed with glass, so the electrical connection between the two electrodes is achieved using a machine using silver bump electrodes as cushioning material. Since it is a physical connection, it has the drawback of causing loose contact in thermal environment atmospheres such as temperature cycle tests and heating tests. The present invention has been made to eliminate such drawbacks, and the object is to obtain an electrode structure that does not cause peeling of the solder material on the back side of the pellet or loose contacts after glass sealing. The gist of the present invention is to provide a silicon substrate with silver bump electrodes formed on one main surface and Cr on the other main surface.
A thin layer of Si and Cr is applied to form a strong adhesive layer. Furthermore, thin layers of Ni and Ag are sequentially deposited to form an electrode structure with excellent thermal stress resistance. Next, the gap between the two electrodes of the Si pellet with the electrode structure formed in this way is
By sandwiching the electrode leads made of Cu material or the like and sealing them with glass, one side of the Si pellets can be
A flexible silver bump electrode is brought into elastic contact with the electrode lead. On the other hand, on the back side, Cr, Ni, and
The Ag laminated electrode is brought into elastic contact with the other electrode lead. As described above, the DHD glass-sealed diode obtained by the present invention has both elastic electrodes with excellent thermal stress in contact with the electrode leads, and is suitable for heat treatment during glass sealing and thermal treatment after glass sealing. A good electrode structure that does not cause loose contact even with respect to the environmental atmosphere can be obtained. Embodiments of the present invention will be described in detail below with reference to the drawings. In FIG. 1, 1 is an N-type silicon substrate,
A P-type conductive layer 2 is formed by diffusion treatment, and a bump electrode 3 is formed on this P-type conductive layer 2. 4 is an insulating protective film covering the surface of the substrate 1, for example, SiO 2 . Thin film layers 5, 6, and 7 of Cr, Ni, and Ag are deposited on the lower surface of the silicon substrate 1 by sequential vapor deposition.
Laminated electrode 8 is formed. The lower surface of the silicon substrate 1 is roughened by etching or sandblasting to increase adhesive strength before the thin film layer is applied thereto. The silicon substrate 1 formed in this structure is separated into individual elements, and pellets 10 are formed. As shown in FIG.
Although not shown, the electrode lead 11 is heated at about 650° C. while being pressurized with a heavy hammer from the upper end of the electrode lead 11 to melt the glass tube 13 and form pellets 1.
0 is sealed. Here, the electrode leads 11 and 12 are generally Fe-Ni core wires coated with Cu, and these leads 11 and 12 generally have an electrode conductor part 14 inside the glass tube and a lead part 15 extending outside. It is designed to have a different diameter than the previous one, and is designed to be suitable for electrode extraction and sealing. The present invention is configured as described above, and strong adhesion between Si of the silicon substrate and Cr to be deposited can be obtained. Here, Cr is a high melting point metal, and Au-Si can be formed by heat treatment during glass sealing as in the past.
- Eliminates the formation of multi-component alloys such as Mg and Au-Si-Ag-Cu, which increases contact resistance and causes contact failure. What is particularly noteworthy here is that the linear expansion coefficient of the Cr-Ni-Ag layer coated on the silicon substrate and in contact with the electrode leads is 0.84 x 10 -5 cm/cm. deg, 1.33×10 -5
cm/cm・deg, 1・97×10 -5 cm/cm・deg Since the metal film is coated with successively larger layers to form a thin film laminated electrode with excellent thermal stress, after heat treatment and sealing for glass sealing. Even in thermal environments such as thermal cycle tests and heating tests, thermal fatigue, deterioration, and defects such as loose contacts can be eliminated. Table 1 shows the results of a comparative test between diode A obtained according to the present invention and conventional diode B.
【表】
第１表に於て、Ａは本発明のDHDガラス封止
ダイオードでペレツト裏面電極をCr−Ni−Ag層
で形成したペレツトを用いたものであり、Ｂは従
来のダイオードで、裏面電極をAu−Ag層で形成
したペレツトを用いたものである。同表から本発
明品は従来のものに比べて、順方向電圧ＶF値が
低く、そのバラツキがいちじるしく改善されてお
り、又ホツトゼツト試験に於いても、ルーズコン
タクト不良の発生率が皆無であり、コンタクト性
のきわめて良好な電極構造であることが確認され
た。裏面電極の各層の厚みはCr層500〜800Å、
Ni層5000〜6000Å、Ag層はNi層より厚く、例え
ば10000Å形成し、各金属層の線膨張係数に対応
して順次厚く形成することにより良好な結果が得
られた。[Table] In Table 1, A is a DHD glass-sealed diode of the present invention using a pellet with a Cr-Ni-Ag layer as the pellet backside electrode, and B is a conventional diode with a backside electrode formed of a Cr-Ni-Ag layer. The electrodes are made of pellets made of Au-Ag layers. The table shows that compared to the conventional product, the forward voltage V F value of the product of the present invention is lower, its variation is significantly improved, and there is no occurrence of loose contact defects in the hot-set test. It was confirmed that the electrode structure had extremely good contact properties. The thickness of each layer of the back electrode is 500 to 800 Å for the Cr layer,
Good results were obtained by forming the Ni layer 5000 to 6000 Å thicker, the Ag layer thicker than the Ni layer, for example 10000 Å, and sequentially forming thicker layers corresponding to the coefficient of linear expansion of each metal layer.
第１図は本発明に係る実施例で半導体装置に使
用されるペレツトの縦断面図、第２図は第１図を
使用して得られるDHDガラス封止ダイオードの
縦断面図である。
３……バンプ電極、８……積層電極、１０……
半導体素子（ペレツト）、１１，１２……電極リ
ード、１３……ガラス管。
FIG. 1 is a vertical cross-sectional view of a pellet used in a semiconductor device in an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a DHD glass-sealed diode obtained using the method shown in FIG. 3... Bump electrode, 8... Laminated electrode, 10...
Semiconductor element (pellet), 11, 12...electrode lead, 13...glass tube.
Claims (1)
子、この半導体素子を挾着する一対の電極リー
ド、及び前記半導体素子と前記一対の電極リード
を外囲し前記電極リードの側面で封着するガラス
管を具備し前記積層電極をCr，Ni，Agの積層に
より形成したことを特徴とするDHDガラス封止
ダイオード。1 Equipped with a semiconductor element having a laminated electrode on at least one side, a pair of electrode leads that clamp the semiconductor element, and a glass tube that surrounds the semiconductor element and the pair of electrode leads and seals them with the sides of the electrode leads. A DHD glass-sealed diode characterized in that the laminated electrode is formed by laminating Cr, Ni, and Ag.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1077279A JPS55103762A (en) | 1979-01-31 | 1979-01-31 | Dhd glass-sealed diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1077279A JPS55103762A (en) | 1979-01-31 | 1979-01-31 | Dhd glass-sealed diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55103762A JPS55103762A (en) | 1980-08-08 |
| JPS623590B2 true JPS623590B2 (en) | 1987-01-26 |
Family
ID=11759615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1077279A Granted JPS55103762A (en) | 1979-01-31 | 1979-01-31 | Dhd glass-sealed diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55103762A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58135942U (en) * | 1982-03-09 | 1983-09-13 | 富士電機株式会社 | glass sealed diode |
| CN106057789A (en) * | 2016-07-01 | 2016-10-26 | 天津中环半导体股份有限公司 | SMD high-voltage silicon stack and production process thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS518871A (en) * | 1974-07-10 | 1976-01-24 | Hitachi Ltd | Handotaisochino denkyoku |
| JPS5165659U (en) * | 1974-11-18 | 1976-05-24 |
-
1979
- 1979-01-31 JP JP1077279A patent/JPS55103762A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55103762A (en) | 1980-08-08 |
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