JPS623593A - Color video signal reproducing device - Google Patents

Abstract

PURPOSE:To correspond to an input having much skew or drop-out and to obtain a reproducing signal of good quality by providing a counter at an address generating circuit which generates an address having the same time base error as a mixing wave and resetting the counter with the timing of a horizontal synchronizing signal separated at a horizontal synchronizing separation circuit. CONSTITUTION:The mixing wave of a modulation luminance signal and a low-pass conversion chrominance signal from a reproducing head 1 is respectively separated at a YC separator 12 and the modulation luminance signal, after demodulated at an FM demodulator 3, is supplied to a storing circuit 51, and the chrominance signal, after separated, is supplied to a storing circuit 52 in the state of a low-pass conversion chrominance signal (fc+ or -DELTAfc CBW). When shift registers are used as storing elements at the storing circuits 51 and 52, the leading edge of a horizontal synchronizing signal HSYNC' generated at a reference synchronizing signal generating circuit 54 is used as the switching timing of a 1H shift register which performs readout, out of several H shares of shift registers. Also, not always resetting the n-ary counter 63 of a write clock address generator 60 with the timing of a horizontal synchronizing signal HSYNC, but it is reset only when the skew or the dropout of the reproducing signal from the reproducing head 1 is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a video tape recorder (hereinafter referred to as a VTR) that records a signal in which an FM-modulated luminance signal and a low frequency-converted carrier chrominance signal are frequency-multiplexed. The present invention relates to a color video signal reproducing device that can be effectively used when converting to a standard television signal during reproduction.

2. Description of the Related Art In a recording medium on which a color video signal is recorded at high density, such as a magnetic tape of a VTR, an FM-modulated luminance signal and a low frequency-converted color signal are usually frequency-multiplexed and recorded. If uneven rotation of the cylinder motor, capstan motor, impedance roller, reel, etc. or longitudinal vibration or expansion/contraction of the tape occurs, this will cause time axis fluctuations in the reproduced color video signal, and these time axis fluctuations will be reflected on the TV screen. This may appear as bending, uneven coloring, or lack of coloring. The output signal of a VTR includes relatively large fluctuations in the time axis, and two methods have conventionally been used to remove this fluctuation in the time axis and obtain a stable color video signal.

One method is to use the AFC and APC characteristics of color monitor televisions to obtain visual images with no temporal axis fluctuations.
The other method is to fundamentally remove time axis fluctuations from the video signal.

The former method is shown in FIG. 6, but in the following explanation,
The luminance signal and color signal to be processed are expressed by a horizontal synchronization frequency fH, a color subcarrier frequency fsc, and a low frequency conversion color subcarrier frequency fc. If the amount of time-axis variation of the reproduced color video signal is ±Δt, and the time-axis variation frequency is fj, the following equation holds true.

Here, ±Δfu+±Δfc and ±Δfsc are frequency fluctuation amounts of each of the signals. Also, the carrier color signal band is ±C
As BW, the carrier color signal is expressed as fscf:Cow.

First, a signal with time axis fluctuations reproduced from the video head 1 is separated into an FM modulated luminance signal and a low frequency converted color signal (fc±Δfe+co*) by the YC separator 2, and then the FM demodulator 3 and the frequency converter 4 respectively. The FM modulated luminance signal is demodulated into a demodulated luminance signal (fu±Δfu), which is supplied to the adder 5. On the other hand, the low-frequency conversion color signal (f
c±Δfc壬CBw) is the carrier color signal (fsc+Csw
), and the frequency fluctuation amount ±Δfc
is canceled out. This process takes place in a loop described below.

First, the color burst extracted by the burst gate 8 from the carrier color signal frequency-converted by the frequency converter 4 is
If the frequency fluctuation of Δfc remains, the phase comparator 9 uses the internal XCO 7 (crystal oscillator with frequency fsc, NTSC
In the case of this method, an error voltage proportional to the frequency difference with the oscillation output (fsc=3.58 MHz), that is, ±Δfc, is generated. This voltage causes the oscillation output of the frequency controlled oscillator 10 to be (
It oscillates at a frequency of fc±Δfc). Therefore, the oscillation output (fc±Δfc) and the oscillation output fsc from the XCO7
is applied to one frequency converter 11 and its output is (fsc+
fc±Δfc), and becomes a signal containing exactly the same time axis fluctuation as the low frequency conversion color signal (fc±Δfc+caw) reproduced from the video head 1. Adding these to the frequency converter 4 results in a stable carrier color signal (fscf Caw)
can be obtained. The tape feeding speed is controlled by a servo circuit 15 that uses a control signal obtained from the tape by a control head 14 and a frame frequency obtained by dividing a vertical synchronization signal generated by a vertical synchronization signal generator 12 by a flip-flop 13. This is done by comparing the rotational speed of the capstan motor 16 and controlling the rotation speed of the capstan motor 16. VT
The R output terminal 6 receives the frequency-converted carrier color signal (f
sc±Cow) and the demodulated luminance signal (fn±Δfu) after passing through the FM demodulation circuit 3 are added by an adder 5 and output as a reproduced color video signal.

As can be seen from FIG. 6, the reproduced color video signal output to the terminal 6 includes time axis fluctuations as is, but the color burst signal maintains the oscillation frequency fsc of the XCO 7,
A visually stable reproduced color video signal is obtained by AFC and Apc of the color monitor. Although the color video signal reproduced by the method described above is color-locked on the color monitor, a dot interleave relationship (for example, in the case of an NTSC television signal, fsc=(455
/2) is lost, and if dubbing from one tape to another is repeated, the time axis fluctuations will be added and the playback screen will deteriorate.

Therefore, the latter method is used to obtain a high quality reproduced color video signal. The latter method uses a reproducing head 1, a YC separator 2, an FM demodulator 3, as shown in FIG. Adder 5, frequency converters 4, 11, burst gate 8, phase comparator 91
In addition to the recording and reproducing section 30 consisting of a frequency controlled oscillator 10° flip-flop 13, a servo circuit 15, a capstan motor 16, and a control head 14, an input terminal 21,
Memory circuit 22, output terminal 29, write clock/address generator 23, read clock address generator 24
, synchronization signal generator 25, advanced composite synchronization signal generator 26, horizontal synchronization separation circuit 17, carrier generation circuit 18,
Reference synchronization signal input terminal 27, reference color subcarrier input terminal 2
8. A time base collector 31 (hereinafter referred to as TBC) consisting of a color subcarrier output terminal 19 and an advanced composite synchronization signal output terminal 20 is required, and the difference in configuration from FIG. The problem lies in the need to send back a carrier wave and a composite synchronization signal.

Incidentally, in FIG. 7, the same parts as in FIG. 6 are given the same reference numerals and symbols, and the explanation thereof will be omitted. Among the color video signals output from the adder 5, the luminance signal has a frequency (fa±Δfo) as in FIG.

The TBC 31 inputs the color video signal from the terminal 21, separates the synchronization signal in the horizontal synchronization separation circuit 17, and multiplies its frequency by 455/2 in the carrier generation circuit 18 to have the same time axis fluctuation as the luminance signal. Color subcarrier fsc±Δ
Create fsc= (455/2) (fa±Δfa). By sending this color subcarrier back from the terminal 19 to the recording/reproducing unit 30 and replacing it with the oscillation output fsc of the XCO 7 shown in FIG. 6, the output of the frequency converter 4 has a different time axis than the luminance signal (fa±Δfu). The carrier color signal (fsc±Δfsc +Cew) with fluctuation is obtained, and the luminance signal (fu±Δfn) and the carrier color signal (fsc±Δfsc
f:, Cew) is added by the adder 5 and output to the terminal 21. Further, as a vertical synchronization signal for controlling the capstan motor 16, a composite synchronization signal is generated by the synchronization signal generator 25 from the reference synchronization signal input from the terminal 27 of the TBC 31 and the reference color subcarrier input from the terminal 28. Further, an advanced composite synchronizing signal generator 26 generates an advanced composite synchronizing signal whose phase is advanced from that of the composite synchronizing signal, and supplies the generated advanced composite synchronizing signal to the flip-flop 13 of the recording/reproducing section 30 through the terminal 20. The main operation of the TBC 31 is to control the luminance signal (fH±Δfu) input from the terminal 21.
) and the carrier color signal (fsc±Δfsc +CBw), the time axis fluctuation is removed by the storage circuit 22,
The mixed wave of the luminance signal fn and the carrier color signal (fsc±Cnw) will be output to the terminal 29, and the method for doing so will be described below. The write clock address generator 23 receives the luminance signal (fu±Δ
fu) and carrier color signal (fsc±Δfsc +CBw)
A clock and an address having the same time axis fluctuation are created from the mixed wave and supplied to the storage circuit 22. Memory circuit 22
Storage elements include analog memories such as switched capacitors and COD, digital shift registers, and R
An AM (random access memory) or the like is used, but if a digital element such as a digital shift register or RAM is used, the storage circuit 22 includes an A/D and D/A converter. The memory circuit 22 writes the mixed wave from the terminal 21 using the tarokku and address having the above-mentioned time axis fluctuation. A synchronization signal generator 25 mixes the reference synchronization signal from terminal 27 and the reference color subcarrier from terminal 28 and provides it to a read clock and address generator 24, which mixes the reference synchronization signal from terminal 27 and the reference color subcarrier from terminal 28, and provides the mixed signal to a read clock and address generator 24, which mixes the reference synchronization signal from terminal 27 and the reference color subcarrier from terminal 28, and provides the mixed signal to a read clock and address generator 24, which mixes the reference synchronization signal from terminal 27 and the reference color subcarrier from terminal 28, and supplies the mixture to a read clock and address generator 24. A clock and an address synchronized with the reference synchronization signal and the reference color subcarrier are generated in the same manner as the address generator 23 and are supplied to the storage circuit 22. By reading out the mixed wave written in the memory circuit 22 using the clock and address synchronized with the reference synchronization signal and the reference color subcarrier, the terminal z9 is synchronized with the reference synchronization signal and the reference color subcarrier, and time axis fluctuations are removed. reproduced color images (for example, the Journal of the Television Society, Vol. 3).
Vol. 0, No. 6 (1981) 495-502).

Problems to be Solved by the Invention As explained above, the latter method is necessary to obtain high-quality reproduced color video signals, but with this conventional configuration,
The luminance signal (f
o±Δfu) has the same time axis variation as the reproduction signal input from the reproduction head 1, but the conveyance color signal (fsc±Δfu)
fsc fcBw) is processed by a phase locked loop (hereinafter referred to as PLL) consisting of a closed loop consisting of a burst gate 8, a phase comparator 9, a frequency controlled oscillator 10, a frequency converter 11, and a frequency converter 4. This is obtained as a result of controlling the frequency fluctuation of the burst of the carrier color signal obtained by the frequency converter 4 to match the frequency fluctuation of the color subcarrier having the time axis fluctuation given from the carrier generation circuit 18. The color subcarrier supplied from this carrier generation circuit 18 is also obtained from the horizontal synchronization signal of the mixed wave supplied to the terminal 21. The frequency signal controlled or created by such a PLL contains a constant steady phase error as jitter due to the delay of the feedback system, and therefore the fsc±Δfsc as described above
= (455/2) (fu±Δfu) does not necessarily hold.

In addition, a clock generated by the write clock/address generator 23 and having the same time axis error as the mixed wave supplied from the terminal 21 is also used for the horizontal synchronization signal of the luminance signal (fu±Δfu) and the carrier color signal (fsc±Δfsc). ±CBW) using a PLL, and has a certain degree of phase error relative to the time axis error of the actual mixed wave. Due to the above-mentioned phase error, the color video signal after passing through the storage circuit 22 has some time axis fluctuation. In particular, since the hue of the carrier color signal changes depending on its phase fluctuation, in order to obtain desired characteristics, the circuit becomes complicated and costs increase.

Furthermore, in order to reduce the phase error of the PLL, its response speed cannot be increased, and it cannot cope with signals with many dropouts or sudden skew distortion. For example, memory circuit 2
A configuration in which several shift registers with a storage capacity of IH (upper horizontal synchronization period) are used as the second storage element, rotated for each IH, and data between IHs is written and then data between IHs is read. If the IH shift register is configured to control writing and reading so that they do not overlap in time, if the horizontal synchronization signal is corrupted by noise or dropout, and cannot be detected, the write clock will be Its frequency slows down over H. On the other hand, since the read clock is constant, the data to be read has not yet been written to the shift register to be read, and a state occurs in which there is no data to be read. Another possible method is to connect the outputs and inputs of IH shift registers in a ring shape during read operations to supplement the same data, but if n is the number of IH shift registers that make up the memory circuit 22, the data from n H previous , there is almost no H correlation in the luminance signal, and the reproduced screen of the obtained video signal becomes unnatural. Furthermore, if a switched capacitor, RAM, or the like is used as the storage element of the storage circuit 22, discontinuous points may occur in read data for the same reason, resulting in skew. In addition, if the write clock speeds up by several H due to input signal joints or skew during special playback, and the write address overtakes the read address, the playback screen may become unnatural or the skew may occur. Causes distortion. Therefore, it is necessary to increase the storage capacity of the storage circuit 22 so as to sufficiently cope with the delay and jitter in the PLL response speed.

Furthermore, the writing or reading speed of the memory circuit 22 requires that its clock frequency be twice the highest frequency of the carrier color signal (fsc±Δfsc±Cow) of the mixed wave supplied from the terminal 21, and If you want to run them in parallel, you need to double their speed or capacity. Therefore, the memory circuit 22 needs to be high-speed and large-capacity, which increases the cost.

Because of the above, the latter time axis variation correction method can only be used in the field of broadcasting equipment, which requires reproduction of extremely high quality color video signals from high quality recording tapes and is not concerned with cost. there were.

In view of the above problems, the present invention provides a TBC as explained above.
The present invention provides a color video signal reproducing device which realizes the following at a low cost, supports input signals with many skews and dropouts, and obtains high-quality reproduced signals.

Means for Solving the Problems In order to solve the above problems, the color video signal reproducing apparatus of the present invention uses YC separation to separate a mixed wave of an FM modulated luminance signal and a low frequency converted color signal extracted from a recording medium. Vessel and F
An M demodulator, a horizontal synchronization separation circuit that separates a horizontal synchronization signal from the demodulated luminance signal after passing through the FM demodulator, two storage circuits, and generates an address with the same time axis error as the mixed wave from the recording medium. A time axis corrector having at least one address generation circuit that operates with a reference clock and an address generation circuit that operates with a reference clock, a frequency converter, and an adder, and after separating the mixed wave with a YC separator, the luminance Regarding the signal, the time axis is corrected using the time axis corrector for the signal demodulated by the FM demodulator, and the time axis is corrected using the time axis corrector for the low frequency converted color signal, and then the predetermined carrier frequency is adjusted using the frequency converter. The demodulated luminance signal after time axis correction and the carrier color signal after frequency and wave number conversion are added in an adder to obtain a color video signal. An address generation circuit that generates an address with a time axis error is provided with a counter, and the counter is reset in accordance with the timing of a horizontal synchronization signal separated by a horizontal synchronization separation circuit.

Operation The present invention has the above-described structure, which simplifies the structure by incorporating a TBC, which has conventionally been used as an external device connected to a VTR, and by creating a reference signal internally.
Furthermore, by performing time axis correction on the carrier color signal in the state of the low-frequency conversion color signal CL, a stable PLL with little steady phase error can be realized with a circuit of simple configuration. Furthermore, by using a low-capacity and low-speed memory circuit, it is possible to obtain the same time axis correction effect as a conventional TBC, and it is also possible to correct signals with many skews and dropouts, which conventional TBCs cannot handle. Realize a video signal reproducing device.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a system diagram of a color video signal reproducing apparatus according to an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and their explanation will be omitted. In FIG. 1, the burst gate 61. AFC/AP
C circuit 62. An n-ary counter 63 (n is a positive integer) constitutes a write clock/address generator 60, and a reference clock generator 71 and an n-ary counter 72 constitute a read clock/address generator 60.
Configure address generator 70. 51 is a storage circuit (1) into which the FM demodulated luminance signal (fo±Δfn) is input.
, 52 is a low-frequency conversion color signal (fc±Δfc-4-Csw)
53 is an xC○ (crystal oscillator), 54 is a reference synchronization signal generator, 55 is a carrier generation circuit, and 56 is a reproduced color video signal output terminal.

In the color video signal reproducing apparatus configured as described above, first, a mixed wave of a modulated luminance signal and a low-frequency conversion color signal from the reproduction head 1 is separated by a YC separator 2, and a modulated luminance signal is separated by an FM demodulator 3. After being demodulated by the storage circuit (1
) 51, and after separation, the color signal is supplied to a storage circuit (2) 52 in the form of a low frequency converted color signal (fc±Δfc壬Csw). Figure 2 shows the memory circuit (1) 51.
, the waveforms of each part related to the input/output waveforms in the memory circuit (2) 52 are shown, and FIG. 3 is a timing chart of each part in the write clock/address generator 60.

A write clock/address generator 60 generates a write clock and a write address for the memory circuit (1) 51 and the memory circuit (2) 52. The operation is first AFC
/APC circuit 62 generates horizontal synchronizing signal HSYNC and horizontal synchronizing signal HSY, which has the same frequency fluctuation rate as the burst of the low frequency converted color signal extracted by burst gate 61;
Create a clock CK having a frequency n times that of NC. The n-ary counter 63 is configured, for example, to count the clock CK and reset the count value at the rising edge of the horizontal synchronizing signal. With this configuration, the write clock/address generation circuit 60 supplies the count value of the n-ary counter 63 to the memory circuit (1) 51 and the memory circuit (2) 52 as the write address W. Here, the tarokk CK has the same time axis fluctuation as the mixed wave from the reproducing head 1, the address W has the same time axis error as the mixed liquid, and maintains a constant value at the rise of the horizontal synchronization signal, Furthermore, it becomes an address that repeats n types of numerical values at the IH period.

When using analog memory or RAM as a storage element, the demodulated luminance signal (fo±Δfu) and low-frequency conversion color signal (fc±
Δfc+caw) is written. When using shift registers as storage elements, several (three or more) with IH storage capacity are used. In this case, the address generation circuit may switch the IH shift register to which writing is performed among several H shift registers for each IH. For example, the shift register may be switched at the timing of the rising edge of the horizontal synchronization signal. Alternatively, the circuit is configured so that the write shift register is switched at a specific address of the n-ary counter 63.

By this method, memory circuit (1) 51, memory circuit (2) 5
The signal (fc±Δfn) written in 2 and the signal (fc
±Afc 1,000 C0W) data is read by frequency-multiplying and frequency-dividing the reference oscillation output from the XCO 53 using the reference clock generator 71 inside the read clock/address generator 7o to create the read clock CK'. A read address R is obtained as a count output of the n-ary counter 72, and the memory circuit (1) 51 and the memory circuit (2) 52 are read using the read address R.

Further, the reference horizontal synchronization signal H is generated by the reference synchronization signal generator 54.
8YNC' is created from the reference oscillation output of the XCO 53, and by detecting the rising edge of the HSYNC' and resetting the count value of the n-ary counter 72, the memory circuit (1) 51 and the memory circuit (2) ) 52, a demodulated luminance signal fH and a low frequency converted color signal (
fe壬Cow) is taken out. Memory circuit (1) 51,
When a shift register is used as the storage element of the storage circuit (2) 52, the horizontal synchronization signal H8Y generated by the reference synchronization signal generator 54 is used as the switching timing of the IH shift register that performs reading out of several H shift registers.
Either the rising edge of NC' is used, or the count output of the n-ary counter 72, that is, the read address R.
The read shift register is switched at a specific address.

Thereafter, the low frequency converted color signal (fo+Csw) is sent to the frequency converter 4 from the carrier generation circuit 55 (fsc+
The carrier color signal (fsc+Caw) is multiplied by f(ri) and frequency-converted to its output.The carrier generation circuit 55 is composed of a frequency divider circuit and a frequency multiplier circuit, and is used for frequency conversion from the reference oscillation output of the XCO53. This is to create a carrier (fga+fc).

The adder 5 receives the extracted carrier color signal (fsc+:C
5w1) and the time-axis corrected demodulated luminance signal fH are added and outputted to the output terminal 56 as a video signal for color television.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows the write clock/address generator 60 of FIG. 1 in the color video signal reproducing apparatus of the present invention.
Instead of constantly resetting the n-ary counter 63 of the playback head 1 at the timing of the horizontal synchronization signal HSYNC,
The write clock is configured to detect skew distortion and dropout of the playback signal from the
3 is a detailed system diagram of the address generator 60. FIG. In FIG. 4, parts having the same functions as those in FIG. 1 are given the same numbers and symbols, and their explanation will be omitted.

Also, the parts other than the write clock/address generator 60 are the same as those in FIG. FIG. 5 shows the timing of each part in FIG. 4.

In FIG. 4, the write clock address generator 6
0 is burst gate 61, AFC/APC circuit 62, n
It consists of a forward counter 63, a comparator 64, flip-flops 65 to 67, and an AND gate 68, and its operation starts from the burst of the low frequency conversion color signal (fe±Δfc+Cow) extracted by the horizontal synchronizing signal H8YNC burst gate 61. A clock CK having the same time axis fluctuation as the signal from the playback head 1 shown in the figure is sent to the AFC/APC circuit 62.
Create with. The frequency of the clock CK is selected to be n times the horizontal synchronization frequency (n is a positive integer), and the frequency of the clock CK is selected to be n times the horizontal synchronization frequency (n is a positive integer).
By counting the clock GK at step 3, the count value, that is, the write address W becomes 0 at the period of IH =
It becomes a read address that repeats the value n - 1,
It is supplied to the memory circuit (1) 51 and the memory circuit (2) 52 in FIG. Further, the comparator 64 and the flip-flops 65 to 67 constitute a detection circuit 80 that detects when the count value of the n-ary counter 63 at the position of the rising edge of the horizontal synchronization signal is outside a certain range.
The ND gate 68 outputs the horizontal synchronizing signal H only when the detection signal E from the detection circuit 80 is at logic level IIH1'.
At the rising edge of S Y N C, the n-ary counter 63
A reset prohibition circuit 81 is configured to reset the count value of . The operation of the detection circuit 80 is to detect the value of the address W from the counter using a comparator. For example, as shown in FIG. 5(a), when the value of the address W is n-3 to n-1,0, the comparator outputs C. The output C is set to output a logic level II HIH, and the output C is latched by a flip-flop 65.
The portion where the output signal F is 11 HII is set as a reset prohibited section. Here, when the AFC/APC circuit 62 is operating stably in a steady state, the write address W from the counter 63 repeats the values 0 to n-1 at the same period of IH as described above, and when the rising edge of H3YNC The signal F is located in the middle of the “HIH” reset prohibition period.The detection signal E is output by the flip-flop 66 to
This signal is an inversion of the signal latched at the rising edge of H3YNC, and is always at the "'L" level. The reset prohibition circuit 81 controls whether or not to reset the n-ary counter 63, and when the detection signal E is "L", the n-ary counter 6 is reset.
The reset manual power CL of No. 3 is always 11 L IH, and the counter 63 is not reset by the horizontal synchronizing signal H5YNC, and the address W is generated according to a determined cycle of the n-ary counter.

In addition, if the reproduction signal from the reproduction head 1 becomes temporally discontinuous due to skew distortion, or if the response of the AFC/APC circuit 62 is disturbed due to dropout, the AFC/APC circuit 62
If the operation of the C circuit 62 becomes unstable,
), the detection signal E becomes "H" at the rising edge of the horizontal synchronizing signal H8YNC. As a result, the n-ary counter 63 registers the address W at the rising edge of the clock CK.
is reset, and the address W becomes O. The AND gate 68 of the reset prohibition circuit 81 outputs the detection signal E and the signal HS.
The logical product of YNC is reset input CL of the n-ary counter 63.
However, the reset operation is also possible by directly using the detection signal E as the reset input, and the signal H3YN
By performing a logical AND with C, the n-ary counter 63 is prevented from being reset erroneously when a thin IIH'' pulse is generated in the signal HSYNC due to noise or a small dropout, for example. C.L.
At the same time as resetting the n-ary counter 63, it is latched by the flip-flop 67 at the rising timing of the clock CK, a signal of 11 L IH is supplied to the flip-flop 66 as the signal PR, and the detection signal E becomes L''. Through this operation, the write clock/address generator 60 detects skew distortion and dropout of the reproduction signal from the reproduction head 1.

Only then does it operate to reset the address W generated by the counter 63 at the timing of the horizontal synchronizing signal HSYNC.

Even if the actual AFC/APC circuit 62 operates stably in the steady state described above, the generated clock CK has a certain steady phase error, and if the steady phase error is large, the write clock CK shown in FIG. address generator 60
As shown in the mapping diagram of FIG. 3, in the configuration shown in FIG. Yes, and at this time, when reading, it must be synchronized with the reference clock CK'.
Since the value of 1 is used as a read address that is repeated in one cycle of the reference horizontal synchronizing signal H8YNC', the memory circuit (1
) 51 and the memory circuit (2) 52, temporal discontinuity occurs near the rising edge of the horizontal synchronization signal, which appears as small skew distortion on the playback screen. In the second embodiment, a detection circuit 80 and a reset prohibition circuit 81 are added to the write clock/address generator 60 to generate the signal H3YN.
By prohibiting the reset of the n-ary counter 63 when the rising edge of C falls within a certain range of the write address.

The steady phase error of the AFC/APC circuit 62 prevents small skew distortion from appearing on the reproduced screen.

In addition, AFC/APC in Figure 1 or Figure 4
The general configuration of the circuit 62 is a so-called AFC operation in which the frequency of the clock CK is controlled by comparing the phases of the horizontal synchronizing signal H5YNC and the frequency-divided signal of the clock CK, and a burst of the low frequency conversion color signal (fc±Δfc+caw). By the APC operation, which compares the phases of the low carrier frequency signal created from the clock CK and the clock CK and controls the oscillation phase of the tarokk CK,
It generates the clock OK, but it also generates the clock C which has the same time axis fluctuation as the reproduction signal from the reproduction head 1.
Another circuit may be used in place of the AFC/APC circuit 62 as long as K can be obtained. For example, the time axis error information is converted into a low frequency converted color signal (fc±Δf) by the APC operation.
It may be created only from bursts of c-)-Cow).

In that case, since the burst of the low frequency conversion color signal is an intermittent wave, the low frequency carrier frequency signal created from the clock CK has a stable point for each horizontal frequency other than the burst frequency, so When a stable point is reached, a separate control circuit is required to detect it and control the clock CK to a normal frequency (hereinafter referred to as sidelock prevention operation). In particular, in the present invention, if the time axis fluctuation of the clock CK created from the horizontal synchronization signal HSYNC by AFC operation causes skew distortion in the reproduction signal from the reproduction head 1, the frequency error detection result will be very large due to the discontinuous portion. If a dropout occurs, the dropout may be mistakenly detected as a horizontal synchronization signal, or conversely, the horizontal synchronization signal may not be detected, resulting in a very large frequency error. If such a very large frequency error is output as a result, it will take a considerable amount of time to return to the normal stable state, and furthermore, it will be impossible to correct small time axis fluctuations during that time. For the above-mentioned reasons, when correcting the time axis of a signal with many skew distortions and dropouts, it is more effective to create the clock CK using the APC operation and sidelock prevention operation.

In the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 4, the write address W generated by the write clock/address generator 60 and the read address R generated by the read clock/address generator 70 are are a memory circuit (1) 51 for the demodulated luminance signal (fH±Δfo) and a memory circuit (2) 5 for the low-frequency conversion color signal (fc±Δfc 1,000 CBw).
For example, the demodulated luminance signal (fu
±Δfn) and low-frequency conversion color signal Cfc±Δfc-)−CB
w) If the frequency difference between the highest frequencies is large, the write clock/address generator 60 and the read clock/address generator 60
The address generator 70 is configured with two clock address generators each for a demodulated luminance signal and a low frequency converted color signal. , the number of addresses for IH for the low frequency conversion color signal (fc±Afo 壬Cow) is smaller than the number of addresses for the demodulated luminance signal (fn±Δfn) to minimize memory. In this case, the write side and the read side each have two counters with different count numbers, and also have two systems each of the write clock CK and read clock CK', and the division ratio or frequency when creating the taro clock. The multiplication ratio is changed so that the period of the address when supplied to each of the counters having different counts is set to IH.

Also, the number of addresses supplied to the memory circuit (2) 52 is set to 1/2, 1/2 of the number of addresses supplied to the memory circuit (1) 51.
If set to 1 in the power of 2 such as /4, the memory circuit (2
) 52 can be used by truncating the lower bits of the address supplied to the memory circuit (1) 51, and one counter can be configured on the writing side and one on the reading side.

Effects of the Invention As described above, the present invention provides FM data taken out from a recording medium.
YC that separates the mixture of modulated luminance signal and low-frequency conversion color signal
A separator, an FM demodulator, a horizontal synchronization separation circuit that separates a horizontal synchronization signal from a demodulated luminance signal after passing through the FM demodulator, two storage circuits, and the same time axis error as the mixed wave from the recording medium. a time axis corrector, a frequency converter, and a frequency converter;
An address generation circuit that includes an adder and generates an address having the same time axis error as the mixed wave has a counter, and is configured to reset the counter based on the timing of the horizontal synchronization signal separated by the horizontal synchronization separation circuit. Therefore, first of all, the write clock is the horizontal synchronization signal H3YNC or the low frequency conversion color signal (fc±Δfc
+ CnW), and the write address is created by a counter that counts the write clock and is created by resetting it with the horizontal synchronization signal H9YNC. Therefore, the write clock/address generator is similar to the conventional example shown in Fig. 7. It can be realized with a comparatively simple configuration. Second, by performing time axis correction in the state of the low-frequency conversion color signal (fc±Afc 1,000 CBw), the steady phase error of the write tarlock and the write address can be adjusted to the horizontal synchronization signal H8YN.
The hue shift and color unevenness on the playback screen caused by discontinuity of the carrier wave that occurs in the part reset with C is compared with when time axis correction is performed using the carrier color signal (f+; c±Δfsc±C0W). It is not noticeable because the amount of phase fluctuation per time is small. Thirdly, write address to horizontal synchronization signal H5
By resetting with YNC, the write address can immediately respond to the skew distortion of the signal input to the memory circuit, which has the effect of correcting skew distortion during reading, and also prevents the write clock from slowing down due to skew distortion or dropout. Even if an overtake or an overtake occurs between the write address and the read address on the storage circuit when Because there is no skew on the playback screen,
In the case of the conventional example shown in FIG. 7, it was necessary to make the storage capacity of the storage circuit sufficiently large in order to avoid overtaking or being overtaken between the write address and the read address on the storage circuit. Efficient time axis correction can be performed using a storage circuit with a large storage capacity.

In addition, in the color video signal of the present invention, the address circuit that generates an address with a time axis error operates its counter with a count value of O-n -1 when the operating clock is n times the horizontal frequency (n is a positive integer). is an n-ary count that is counted every horizontal period, and further includes a detection circuit that detects when the count value of the counter with respect to the position of the horizontal synchronization signal exceeds a certain range, and a detection circuit that detects this and determines the timing of the horizontal synchronization signal based on the detection result. By providing a reset prohibition circuit that controls whether or not to reset the counter, when the write clock is generated stably, the write address W is reset by the horizontal synchronization signal H3YNC. Due to the reset operation of the address W described above, the time-base corrected signals in the memory circuit (1) 51 and the memory circuit (2) 52 cause discontinuity near the horizontal synchronization signal, causing a discontinuity on the playback screen. It is possible to prevent the appearance of fine skews.

As a result of the above-mentioned effects, the color video signal reproducing device of the present invention can remove time axis fluctuations in the reproduced color video signal with an extremely inexpensive circuit and obtain a high quality color video signal, making it extremely useful in practice. be.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a color video signal reproducing device according to a first embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams of various parts in FIG. A detailed system diagram of the main parts of the color video signal reproducing device in the example, FIG. 5 is a waveform diagram of each part in FIG. 4, and FIGS. 6 and 7 are system diagrams of the conventional color video signal reproducing device. be. 1... Playback head, 2... YC separator, 3... F
M demodulator, 4... frequency converter, 5... adder, 1
7...Horizontal synchronization separation circuit, 51...Memory circuit (1)
, 52... memory circuit (2), 53... xco, 5
4... Reference synchronization signal generator, 55... Carrier generation circuit, 56... Output terminal, 60... Write clock/address generator, 61... Burst gate, 62
・AFC/APC circuit, 63.72-N-ary counter, 70... Read clock/address generator, 71... Reference clock generator, 80... Detection circuit, 81... Reset Prohibited circuit agent Yoshihiro Morimoto Figure S, a1

Claims (1)

[Claims] 1. A YC separator that separates a mixed wave of an FM modulated luminance signal and a low frequency converted color signal extracted from a recording medium, an FM demodulator, and a demodulated luminance signal after passing through the FM demodulator. a horizontal synchronization separation circuit that separates a horizontal synchronization signal from the two storage circuits, an address generation circuit that generates an address having the same time axis error as the mixed wave from the recording medium, and an address generation circuit that operates with a reference clock. The address generation circuit includes at least one time base corrector, one frequency converter, and one adder, and further includes a counter for generating an address having the same time base error as the mixed wave, and horizontal synchronization separation. A color video signal reproducing device configured to reset the counter according to the timing of a horizontal synchronization signal separated by a circuit. 2. An address circuit that generates an address with a time axis error must operate a counter whose operating clock is n times the horizontal frequency (
n is a positive integer), and the count value from 0 to n-1 is counted every horizontal period. Claim 1, characterized in that it is equipped with a detection circuit that detects the above-mentioned counter, and a reset prohibition circuit that controls whether or not to reset the counter at the timing of the horizontal synchronization signal based on the detection result.
The color video signal reproducing device as described in .