JPS623603U

JPS623603U -

Info

Publication number: JPS623603U
Application number: JP9311685U
Authority: JP
Priority date: 1985-06-20
Filing date: 1985-06-20
Publication date: 1987-01-10

Description

[Brief explanation of the drawing]

第１図は本考案実施例の回路ブロツク図、第２
図、第３図は動作説明のための図である。２……消去兼再生ヘツド、３……記録兼消去ヘ
ツド、４……再生兼記録ヘツド、８……再生回路
、９……記録回路、１０……バイアス発振回路、
１３……遅延手段、１６……制御回路。 Fig. 1 is a circuit block diagram of an embodiment of the present invention;
FIG. 3 is a diagram for explaining the operation. 2... Erasing and reproducing head, 3... Recording and erasing head, 4... Reproducing and recording head, 8... Reproducing circuit, 9... Recording circuit, 10... Bias oscillation circuit,
13... Delay means, 16... Control circuit.

Claims

[Scope of utility model registration request]

A playback head is placed furthest in front of the running magnetic tape, an erase head is placed a first distance behind the playback head, and an erase head is placed a second distance behind the erase head and a second distance from the playback head. an erasing means for arranging a recording head arranged on the magnetic tape, and performing an erasing operation on the erasing head with a delay of time related to the first distance after the reproduction head reaches a certain point on the magnetic tape; A magnetic recording/reproducing apparatus comprising a recording means for delaying the output by a time related to the second distance and subjecting the output to fade-in processing, fade-out processing, or mixing processing with another signal and supplying the resultant to the recording head.