JPS6236861A - High speed semiconductor device - Google Patents

Abstract

PURPOSE:To perform the original high rapidity as an HET according to the present MBE technique by providing a compound semiconductor base layer for generating a gas layer by electrons or holes transferred from a compound semiconductor emitter layer, and the compound semiconductor emitter layer for implanting electrons or holes to the base layer. CONSTITUTION:When an N-type Al0.5Ga0.5As emitter layer 14 and an N-type GaAs base layer 13 are laminated, electrons in the layer 14 are transferred to the layer 13 to generate an electron gas layer 20, and a potential barrier is generated in a boundary. When the layer 13 is set to positive (+) and the layer 14 is set to negative (-) to be applied with a bias voltage to an operating state, the bottom EC of a conduction band of the layer 14 increases to cause electrons from the layer 14 to readily override or tunnel the potential barrier to be implanted to the layer 13, where to become hot electrons to pass the layers 13 and an isolating layer 12, thereby arriving at a collector layer 11.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a compound semiconductor base layer in which a gas layer is generated by electrons or holes from a compound semiconductor emitter layer, and a compound semiconductor base layer in a high-speed semiconductor device. a compound semiconductor emitter layer in which a potential barrier is generated near the heterointerface of the compound semiconductor emitter layer, and when a bias voltage is applied, the conduction band or valence band is raised or lowered to inject electrons or holes into the compound semiconductor base layer. This structure ensures reliable operation and high performance, and can be easily manufactured using current MBE technology.

[Industrial application field]

The present invention is a hot electron transistor (ho
telectron transistor:H
This invention relates to improvements in high-speed semiconductor devices called ET.

[Conventional technology]

Figure 4 shows the conventional A, (l G a A s / G
It represents an energy node diagram for explaining the operation of an aAs-based heterojunction HET.

In the figure, 1 is an n-type GaAs emitter layer, 2 is a non-doped Aj! A GaAs emitter side potential barrier layer, 3 an n-type GaAs base layer, 4 a non-doped Al1GaAs collector side potential barrier layer,
5 is the n-type GaAs collector layer, E□ is the pseudo-Fermi level at the emitter, EFll is the pseudo-Fermi level at the base, El-9 is the pseudo-Fermi level at the collector, and e is the Al1GaAs emitter side potential.・Ho Nodo Electron tunneled through Tsumariya Layer 2, ΔEc is AI! The conduction band energy difference between GaAs and GaAs is shown.

In such a HET, a collector layer 5 and an emitter layer 1
With a bias voltage applied between
) when a voltage of side potential・
tunneled through the barrier layer 2 and injected into the base layer 3;
There, the potential energy of the electron e is converted into kinetic energy, becomes a high-speed hot electron, and is injected into the collector layer 5 over the collector-side potential barrier layer 4 without being scattered.

[Problem that the invention seeks to solve]

In the conventional example explained with reference to FIG.
The probability that electrons tunnel through the emitter-side potential barrier layer 2, which is a barrier, greatly depends on the thickness and height of the barrier and is delicate, so controlling the tunneling current is not so easy.

Also, to increase the tunneling current density, a high voltage must be applied to the base, which increases the kinetic energy of the injected electrons and makes them less susceptible to inter-valley scattering. This results in a decrease in the delivery rate to the collector.

The present invention provides a high-speed semiconductor device that can be easily manufactured by applying current MBE technology.

[Means for solving problems]

The energy band gap is narrower than that of a compound semiconductor emitter layer (for example, n-type AA!o, s Gao, s As emitter layer 14), and the electron or hole affinity is greater than that of the compound semiconductor emitter layer. A compound semiconductor base layer (for example, n-type GaAs base layer 13) in which a gas layer (for example, electron gas layer 20) is generated by electrons or holes transferred from the compound semiconductor emitter layer due to
Then, a potential barrier is generated in the vicinity of the hetero interface due to the action of the positive or negative charges that remain due to the transfer of electrons or regular charges formed in contact with the compound semiconductor base layer to the compound semiconductor base layer, resulting in a bias. A compound semiconductor emitter that injects electrons or holes into the compound semiconductor base layer by raising or lowering the bottom of the conduction band (for example, EC) or the top of the valence band (for example, EV) when a voltage is applied.
It has a structure comprising an ivy layer.

[Effect]

According to the above configuration, the generation of a potential distribution within the semiconductor device, which is one of the factors for achieving high performance, depends on the steepness of the heterojunction and the doping amount of the donor or acceptor, which is difficult to achieve in the current MBB. This can be realized in a well-controlled manner depending on the technology.

〔Example〕

FIG. 1 shows a cutaway side view of essential parts of an embodiment of the present invention.

In the figure, 11 is an n-type QaAs substrate, 12 is a non-doped A Ito, S G 86.7 A 3 isolation layer, 13 is an n-type GaAs base layer, and 14 is an n-type Aj! o, s Ga6,5 As emitter layer, 15 represents an emitter electrode, 16 represents a base electrode, and 17 represents a collector electrode, respectively.

In this embodiment, the isolation layer 12 is attached to the substrate 11.
Its thickness is approximately 1,500 cm. In addition, the base layer 13
Its thickness is approximately 500 cm. Furthermore, the emitter layer 14 has a thickness of about 1,500 [people]. Each electrode is made of gold (Au)/germanium (Ge)/Au, and the thickness of the base electrode 16 is approximately 2006)/2
It is about 000 (people).

Figure 2 shows an energy band diagram in the thermal equilibrium state of the semiconductor device explained in Figure 1, and the same symbols as those used in Figure 1 represent the same parts or have the same meaning. shall be.

In the figure, 20 is the electron gas layer, EC is the bottom of the conduction band, and E
V is the top of the valence band, EBI, EB2. EB3 shows the energy band gear knob, respectively. In this example, EB1=2 (eV) EB2=1.45 (eV) EB3-1.8 (eV).

FIG. 3 shows an energy band diagram in the operating state of the semiconductor device explained with reference to FIG.
The same symbols as those used in the figures and FIG. 2 represent the same parts or have the same meaning.

The operation of the semiconductor device shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

As seen in FIG. 1, n-type Afio, 5 Ga0.
When the 5AS emitter layer 14 and the n-type GaAs base layer 13 are laminated, the electron affinity in the base layer 13 is greater than that in the emitter layer, so as shown in FIG. Electrons in layer 14 are in base layer 1
3 to generate an electron gas layer 20, and a potential barrier is generated at the interface between the emitter layer 14 and the base layer 13 due to the action of the positive charges remaining in the emitter layer 14. Therefore, as shown in Figure 3, the base layer 1
3 to (+) and emitter layer 14 to (-) and apply a bias voltage to bring it into operation, the emitter layer 14
The bottom EC of the conduction band becomes high, and electrons from the emitter layer 14 easily cross the potential barrier generated on the emitter layer 14 side at the interface between the emitter layer 14 and the base 113, or tunnel. and base layer 1
3, where they become electrons, pass through the base layer 13 and the isolation layer 12, and reach the collector layer 11.

Since the potential distribution in the semiconductor device described above depends only on the steepness of the heterojunction and the amount of donor doping, it can be handled with sufficient controllability by applying current MBE technology.

Incidentally, in the above embodiments, a semiconductor device that uses impurities as donors and utilizes the movement of electrons has been described, but the present invention can also be implemented in semiconductor devices that use impurities as acceptors and utilize the movement of holes. I can do it. In that case, all n-type semiconductor layers become p-type semiconductor layers, and the second
Of course, the energy hand diagrams shown in Figures 3 and 3 are all reversed.

〔Effect of the invention〕

In the high-speed semiconductor device according to the present invention, the energy band
A gas layer is generated by electrons or holes transferred from the compound semiconductor emitter layer due to the fact that the gap is narrower than that of the compound semiconductor emitter layer and the affinity for electrons or regular tags is greater than that of the compound semiconductor emitter layer. A potential is generated near the hetero interface due to the action of the compound semiconductor base layer and the positive or negative charges formed in contact with the compound semiconductor base layer and remaining due to the transfer of electrons or holes to the compound semiconductor base layer. - A compound semiconductor emitter layer in which a barrier is generated and which raises or lowers the bottom of the conduction band or the top of the valence band to inject electrons or holes into the compound semiconductor base layer when a bias voltage is applied is adopted. ing.

According to this configuration, in order to generate the potential distribution as shown in FIGS. 2 and 3, for example, only the steepness of the heterojunction and the amount of donor doping are required. Such can be accomplished in a well-controlled manner with current MBE technology. Therefore, there is no difficulty in manufacturing the semiconductor device of the present invention, and the obtained semiconductor device reliably operates at the original high speed as a HET.

[Brief explanation of drawings]

FIG. 1 is a cutaway side view of essential parts of an embodiment of the present invention, FIG. 2 is an energy band diagram in a thermal equilibrium state of the embodiment explained with reference to FIG. 1, and FIG. FIG. 4 shows an energy band diagram for a conventional HET. In the figure, 11 is an n-type GaAs substrate, 12 is a non-doped ANo, s Ga(,, As isolation layer,
13 is an n-type GaAs base layer, 14 is an n-type Aj! o,s
Gao, s AsI emitter layer, 15 is an emitter electrode,
16 is a base electrode, 17 is a collector electrode, and 20 is an electron gas layer. Figure 1. Energy band diagram in thermal equilibrium state. Figure 2. Energy hunt diagram in operating state.
figure

Claims (1)

[Claims] Due to the fact that the energy band gap is narrower than that of the compound semiconductor emitter layer and the electron or hole affinity is greater than that of the compound semiconductor emitter layer, transition from the compound semiconductor emitter layer occurs. A compound semiconductor base layer in which a gas layer is generated by the electrons or holes generated, and a positive charge formed in contact with the compound semiconductor base layer and remaining due to the transfer of electrons or holes to the compound semiconductor base layer. Alternatively, a compound that generates a potential barrier near the hetero interface due to the action of negative charge, raises or lowers the bottom of the conduction band or the top of the valence band when a bias voltage is applied, and injects electrons or holes into the compound semiconductor base layer. A high-speed semiconductor device comprising a semiconductor emitter layer.