JPS6237329U - - Google Patents
Info
- Publication number
- JPS6237329U JPS6237329U JP12622785U JP12622785U JPS6237329U JP S6237329 U JPS6237329 U JP S6237329U JP 12622785 U JP12622785 U JP 12622785U JP 12622785 U JP12622785 U JP 12622785U JP S6237329 U JPS6237329 U JP S6237329U
- Authority
- JP
- Japan
- Prior art keywords
- control program
- main device
- disabled
- turned
- power switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Power Sources (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案による一実施例の回路構成図、第３図は従来
のブロツク図を示す。
図において、１は主装置、２は周辺装置、３は
制御プログラム、４はビツトメモリ部、５はスイ
ツチ回路、６は第１の電源スイツチ、７は第２の
電源スイツチを示す。
FIG. 1 is a basic block diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a conventional block diagram. In the figure, 1 is a main device, 2 is a peripheral device, 3 is a control program, 4 is a bit memory section, 5 is a switch circuit, 6 is a first power switch, and 7 is a second power switch.
Claims (1)
する主装置１と、 該主装置１に接続され、該制御プログラム３に
よつて制御される周辺装置２と、 該主装置１および該周辺装置２のそれぞれに供
給電源ＰＷが投入または切断される第１と第２の
電源スイツチ６，７とを備えると共に、 該ジヨブの実行状態により該制御プログラム３
を介して、ロツク指令、および、ロツク解除指令
が送出されるビツトメモリ部４と、 該第１の第２の電源スイツチ６，７のそれぞれ
の切断制御は該ロツク状態では無効となり、該ロ
ツク解除状態では有効となるスイツチ回路５とが
設けられたことを特徴とする供給電源の誤切断防
止装置。[Claims for Utility Model Registration] A main device 1 having a control program 3 for controlling a predetermined job, a peripheral device 2 connected to the main device 1 and controlled by the control program 3, and the main device 1 and the peripheral device 2, respectively, are provided with first and second power switches 6, 7 through which the power supply PW is turned on or off, and the control program 3 is turned on or off depending on the execution state of the job.
The bit memory unit 4 to which the lock command and the lock release command are sent through the lock command and the disconnection control of the first and second power switches 6 and 7 are disabled in the locked state, and are disabled in the unlocked state. This device is characterized in that it is provided with a switch circuit 5 which becomes effective.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12622785U JPS6237329U (en) | 1985-08-19 | 1985-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12622785U JPS6237329U (en) | 1985-08-19 | 1985-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6237329U true JPS6237329U (en) | 1987-03-05 |
Family
ID=31019831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12622785U Pending JPS6237329U (en) | 1985-08-19 | 1985-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237329U (en) |
-
1985
- 1985-08-19 JP JP12622785U patent/JPS6237329U/ja active Pending