JPS6237360U - - Google Patents
Info
- Publication number
- JPS6237360U JPS6237360U JP12833185U JP12833185U JPS6237360U JP S6237360 U JPS6237360 U JP S6237360U JP 12833185 U JP12833185 U JP 12833185U JP 12833185 U JP12833185 U JP 12833185U JP S6237360 U JPS6237360 U JP S6237360U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- memory
- output
- logical sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Image Processing (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は本考案の適用例を示すブロツク図、第３図は
従来のデータ間引き装置を示すブロツク図。
符号の説明、１０，１１……オア回路、１２…
…バツフア、１３……ラツチ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a block diagram showing an example of application of the present invention, and FIG. 3 is a block diagram showing a conventional data thinning device. Explanation of symbols, 10, 11...OR circuit, 12...
...Batsuhua, 13...Ratsuchi.
Claims (1)
を間引きするデータ間引き装置において、 １ライン分のデータを間引き率に応じてドツト
方向の論理和をとる第１のオア回路と、 該オア回路より出力されるデータと該オア回路
によつて既に処理されているデータとの論理和結
果を格納するメモリと、 該メモリよりのデータを一時的に保持するラツ
チと、 該ラツチの出力と前記第１のオア回路の出力と
の論理和をとつて前記メモリに出力する第２のオ
ア回路を設けたことを特徴とするデータ間引き装
置。[Claim for Utility Model Registration] In a data thinning device that thins out m lines of data, each line consisting of n dots, a first OR circuit that performs a logical sum in the dot direction on one line of data according to a thinning rate. a memory for storing a logical sum result of data output from the OR circuit and data already processed by the OR circuit; a latch for temporarily holding data from the memory; and a latch for temporarily holding data from the memory. A data thinning device characterized in that a second OR circuit is provided for calculating the logical sum of the output of the first OR circuit and the output of the first OR circuit, and outputting the result to the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12833185U JPS6237360U (en) | 1985-08-22 | 1985-08-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12833185U JPS6237360U (en) | 1985-08-22 | 1985-08-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6237360U true JPS6237360U (en) | 1987-03-05 |
Family
ID=31023903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12833185U Pending JPS6237360U (en) | 1985-08-22 | 1985-08-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237360U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS581275A (en) * | 1982-06-14 | 1983-01-06 | Hitachi Ltd | Shading circuit |
-
1985
- 1985-08-22 JP JP12833185U patent/JPS6237360U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS581275A (en) * | 1982-06-14 | 1983-01-06 | Hitachi Ltd | Shading circuit |
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