JPS6237928A - Metallic pattern forming method - Google Patents
Metallic pattern forming methodInfo
- Publication number
- JPS6237928A JPS6237928A JP17796285A JP17796285A JPS6237928A JP S6237928 A JPS6237928 A JP S6237928A JP 17796285 A JP17796285 A JP 17796285A JP 17796285 A JP17796285 A JP 17796285A JP S6237928 A JPS6237928 A JP S6237928A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- lift
- plasma
- pattern
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 5
- 229910001111 Fine metal Inorganic materials 0.000 abstract description 5
- 230000001678 irradiating effect Effects 0.000 abstract description 2
- 238000009832 plasma treatment Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 7
- 239000004926 polymethyl methacrylate Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- CERQOIWHTDAKMF-UHFFFAOYSA-M Methacrylate Chemical compound CC(=C)C([O-])=O CERQOIWHTDAKMF-UHFFFAOYSA-M 0.000 description 1
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 1
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical compound ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、リフトオフ技法によって半導体素子の微細な
電極、配線を形成する金属パターン形成方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a metal pattern forming method for forming fine electrodes and wiring of a semiconductor element by a lift-off technique.
従来の技術
半導体素子の微細化につれて、微細な金属パターンを形
成する技術が重要となっている。従来から、微細な金属
パターンの形成にはリフトオフ法が用いられている。第
２図に、リフトオフを用いた金属電極の形成方法を、従
来例に基づいて説明する。第２図ａに示すように、半導
体基板１上にレジストパターン２を形成した後、同図す
に示すように、０２プラズマ６を用いてライトアッシン
グを行う。その後、第２図Ｃに示すように、金属４を蒸
着し、ついで、リフトオフにより、同図ｄに示す金属電
極５を形成する。2. Description of the Related Art As semiconductor devices become smaller, techniques for forming fine metal patterns are becoming more important. Conventionally, a lift-off method has been used to form fine metal patterns. With reference to FIG. 2, a method for forming metal electrodes using lift-off will be explained based on a conventional example. As shown in FIG. 2a, after forming a resist pattern 2 on the semiconductor substrate 1, light ashing is performed using 02 plasma 6 as shown in the same figure. Thereafter, as shown in FIG. 2C, a metal 4 is deposited, and then by lift-off, a metal electrode 5 shown in FIG. 2D is formed.
発明が解決しようとする問題点
この従来例において問題となるのは、金属を蒸着すると
きに、レジストの温度が上昇することにより、レジスト
が軟化変形して、パターン幅が変化し、甚しくは、パタ
ーンがレジストにより埋められて消失することである。Problems to be Solved by the Invention The problem with this conventional example is that when metal is vapor deposited, the temperature of the resist increases, causing the resist to soften and deform, changing the pattern width, and causing serious problems. , the pattern is filled with resist and disappears.
浄た、レジスト残渣を除去して、半導体基板表面を清浄
にするために用いられている、０２プラズマ処理は、反
面では、レジストの耐熱性を劣化させるという難点があ
り、この問題の解決も望１３へ−
れていた。本発明はこのような問題点を解決するもので
ある。The 02 plasma treatment, which is used to clean the surface of semiconductor substrates by removing resist residue, has the disadvantage of deteriorating the heat resistance of the resist, and a solution to this problem is desired. I was at 13. The present invention solves these problems.
問題点を解決するだめの手段
本発明は、基板上に形成された所定形状のレジストパタ
ーンに、レジストの膜減り量が所定量。Means for Solving the Problems The present invention provides a resist pattern having a predetermined shape formed on a substrate so that the resist film is reduced by a predetermined amount.
最適には、０．１μｍ以内となる時間のあいだ、Ｆまた
はＣｄを含むプラズマを照射した後、金属を蒸着し、つ
いで、レジストと共にリフトオフする工程をそなえだ金
属パターン形成方法である。The most suitable method is a metal pattern forming method that includes the steps of irradiating plasma containing F or Cd for a time period of 0.1 μm or less, then vapor depositing metal, and then lifting off together with the resist.
作 用
本発明を用いることによシ、レジストパターンの耐熱性
が、Ｆまたはｃ６プラズマを照射しない場合に比べて向
上し、しかもレジスト残渣を除去して、半導体基板表面
を清浄に保つことができるので、金属の蒸着およびリフ
トオフが確実、容易となり、微細な金属電極の形成が可
能となる。By using the present invention, the heat resistance of the resist pattern is improved compared to the case where F or C6 plasma is not irradiated, and the resist residue can be removed to keep the semiconductor substrate surface clean. Therefore, metal vapor deposition and lift-off become reliable and easy, and it becomes possible to form fine metal electrodes.
実施例
本発明の実施例について、以下に、第１図の工程順断面
図を参照して説明する。第１図ａに示すように、半導体
基板１上にレジストパターン２を形成した後、同図すに
示すように、レジストの膜減り量が０．１μｍ以内とな
る時間のあいだ、フッを
素（Ｆ）または塩素（Ｃｆｆ）を含むプラズマ９照射す
する。その後、第２図ｃＫ示すように、金Ｒ４を蒸着し
、リフトオフにより金属電極５を形成する。Embodiment An embodiment of the present invention will be described below with reference to step-by-step sectional views of FIG. As shown in FIG. 1a, after forming a resist pattern 2 on a semiconductor substrate 1, as shown in FIG. F) or plasma 9 containing chlorine (Cff). Thereafter, as shown in FIG. 2cK, gold R4 is vapor deposited and a metal electrode 5 is formed by lift-off.
第１の実施例として電子ビーム露光用（ＥＢ）レジスト
のポリメチルメタクリレ−） （ＰＭＭＡ）を用いる場
合について詳細に説明する。Ｇ ａ Ａ ｓ基板上に０
．５μｍの厚さのＰＭＭＡを塗布し、１７０°Ｃ，３０
分間のプリベ−りを行う。露光量６４、μＣ／ｃＩＪＩ
で、露光を行い、メチルイソブチルケトン（ＭＩ ＢＫ
）を用いて２分間現像することにより、開口幅が０．
３μｍのパターンを形成する。次に、円筒形プラズマエ
ツチング装置を用い、ＲＦパワー１５Ｗ、圧力０．４
Ｔｏｒｒ 、ガ−’＜ ＣＦ４ ／ ５係０２の条件で
３ｏ秒間プラズマ処理を行った。As a first example, a case in which polymethyl methacrylate (PMMA) as an electron beam exposure (EB) resist is used will be described in detail. 0 on the Ga As substrate
．． Coat PMMA with a thickness of 5 μm and heat at 170°C, 30
Perform a pre-basis for 1 minute. Exposure amount 64, μC/cIJI
After exposure, methyl isobutyl ketone (MI BK
) for 2 minutes, the opening width becomes 0.
A 3 μm pattern is formed. Next, using a cylindrical plasma etching device, RF power was 15 W, pressure was 0.4
Plasma treatment was performed for 30 seconds under the following conditions: Torr, Gar'< CF4/5.
その処理でのＰＭＭＡの膜減り量は０．１μｍ未満であ
った。その後、電子ビーム蒸着装置を用いて、Ｔｉ／Ｐ
ｔ／Ａｕの三層を、Ｔｉ３００人、Ｐｔ１５００Ａ 、
Ａｕ ３２００ Ａの厚さでそれぞれ蒸着し、っ６、
、−７
いで、ＰＭＭＡと共にリフトオフすることにより、Ｔ
ｉ ／ Ｐ ｔ ／ Ａｕ三層膜による電極幅０．３ｐ
ｍのゲート電極を形成する。The amount of PMMA film reduced by this treatment was less than 0.1 μm. After that, using an electron beam evaporation device, Ti/P
Three layers of t/Au, 300 Ti, 1500 Pt,
Au was deposited to a thickness of 3200 A, respectively.
, -7, and by lifting off with PMMA, T
Electrode width 0.3p by i/Pt/Au three-layer film
m gate electrodes are formed.
ＣＦ４／ ５％ ０２プラズマ処理を行わない場合は、
リフトオフが不可能となる。その理由は、Ｐｔの融点が
１７７３°Ｃと高いために、ｐｔを蒸着する際にレジス
トパターンが変形するからである。If CF4/5% 02 plasma treatment is not performed,
Lift-off becomes impossible. The reason for this is that since the melting point of Pt is as high as 1773° C., the resist pattern is deformed when Pt is deposited.
第３図に、ＰＭＭＡレジストの耐熱性を示す。FIG. 3 shows the heat resistance of PMMA resist.
ＣＦ４７６％０２プラズマ処理により特性Ａのように、
耐熱性が向上することζ逆に０２プラズマ処理では特性
Ｂのように、耐熱性が悪化し、未処理の場合の特性Ｃよ
りさらに悪くなることがわかる。As shown in characteristic A by CF476%02 plasma treatment,
It can be seen that the heat resistance is improved.ζOn the contrary, with the 02 plasma treatment, the heat resistance deteriorates as shown in characteristic B, and is even worse than characteristic C in the case of no treatment.
プラズマ処理の際、ＣＦ４をＣＣｌ４に代えても同様の
効果がある。Similar effects can be obtained by replacing CF4 with CCl4 during plasma treatment.
他のＥＢレジスト、たとえばダイキン社製商品名ＦＢＭ
−Ｇ（ポリへキサフロロブチルメタクリレート）などに
ついても、同じように、ＦｉたはＣｌを含むプラズマ処
理により耐熱性が向上した。Other EB resists, such as Daikin product name FBM
-G (polyhexafluorobutyl methacrylate) and the like were similarly improved in heat resistance by plasma treatment containing Fi or Cl.
つぎに、第２の実施例として、ホトレジストの０ＦＰＲ
８００（東京応化社製）を用いる場合に６１・−。Next, as a second example, 0FPR of photoresist
61.- when using 800 (manufactured by Tokyo Ohka Co., Ltd.).
ついて、より詳細に説明する。Ｓｉ基板上に１．２μｍ
の厚さく７）ＯＦＰＲ８００を塗布し、８５°Ｃｌ２Ｏ
分間プリベークを行う。ステッパーを用いて、１ｏｏｒ
ｎｌ／ｃｒ！の露光を行い、開口幅０．８μｍのパター
ンを露光し、専用現像液である商品名ＮＭＤ−３（東京
応化）を用いて１分間現像することにより、レジストパ
ターンを形成する。次に、円筒形プラズマエツチング装
置を用いて、ＲＦパワー１５Ｗ、圧力０．４Ｔｏｒｒ、
ガスＣ２ＨＣｌ３１５チｏ２の条件で３０秒間、プラズ
マ処理を行った。This will be explained in more detail. 1.2μm on Si substrate
7) Apply OFPR800 to a thickness of 85°Cl2O
Pre-bake for a minute. 1oor using a stepper
nl/cr! A resist pattern is formed by exposing a pattern with an opening width of 0.8 μm and developing for 1 minute using a special developer, trade name NMD-3 (Tokyo Ohka). Next, using a cylindrical plasma etching device, an RF power of 15 W, a pressure of 0.4 Torr,
Plasma treatment was performed for 30 seconds under the conditions of gas C2HCl315Cio2.
このときの膜減り量も０．１μｍ未満であった。その後
、ＥＢ蒸着装置を用いて基板を２００’Ｃに加熱して、
ＡＩを蒸着し、リフトオフすることによりＡＩ！配線パ
ターンを形成した。The amount of film reduction at this time was also less than 0.1 μm. After that, the substrate was heated to 200'C using an EB evaporation device,
By depositing AI and lifting off, AI! A wiring pattern was formed.
第４図に０ＦＰＲａｏｏの耐熱性を示す。FIG. 4 shows the heat resistance of 0FPRaoo.
Ｃ２ＨＣｌ３／６％ｏ２プラズマ処理することにより、
特性りのように耐熱性が向上し、２ｏｏ′Ｃに基板を加
熱してＡＩを蒸着してもパターン幅が変化しない。図中
、特性（Ｅ）は未処理の場合のものである。By C2HCl3/6%O2 plasma treatment,
As a characteristic, heat resistance is improved, and the pattern width does not change even if the substrate is heated to 2oo'C and AI is evaporated. In the figure, characteristic (E) is for the untreated case.
７ ′＼−７
なお、プラズマ処理のＲＦ比出力プラズマ処理時間であ
るが、レジストの膜減りが０．１μｍ以上になる場合は
プラズマ処理による耐熱性向上の効果が弱まった。この
理由は、長時間の処理により、プラズマ処理されたレジ
スト表面がエツチングにより除去されるためであると推
定できる。7'\-7 Regarding the RF specific output plasma processing time of the plasma processing, when the resist film reduction was 0.1 μm or more, the effect of improving heat resistance by the plasma processing was weakened. The reason for this is presumed to be that the plasma-treated resist surface is removed by etching due to the long-time treatment.
発明の効果
以上に詳述したように、本発明を用いることにより、半
導体基板表面に残存するレジスト残渣を除去して、しか
もレジストの耐熱性を向上させることが可能となるので
、微細金属電極を容易に、リフトオフにより形成するこ
とができる。Effects of the Invention As detailed above, by using the present invention, it is possible to remove resist residue remaining on the surface of a semiconductor substrate and improve the heat resistance of the resist. It can be easily formed by lift-off.
第１図ａ ％ ｄは本発明の実施例の工程順断面図、第
２図ａ −ｄは従来例の工程順断面図、第３図は本発明
実施例によるＰＭＭＡの耐熱性を示す特性図、第４図は
本発明実施例による０ＦＰＲｓｏ。
の耐熱性を示す特性図である。
１・・・・・半導体基板、２・・・・・・レジストパタ
ーン、３・・・・・・ＦまたはＣＩを含むプラズマ、４
・・・・・・金属、６・・・・・・金属電極、６・・・
・・・ｏ２プラズマ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第３
図
Ａ〜−−ＣＦｑ９％θ２ブラズーフ々珪Ｂ −−−Ｄｔ
７−ラスマ舛理
Ｃ−−−袈（成
情処理遥／￥ｃ６ｃ）
粥４図
Ｄ−−−Ｃ２Ｈα３／、ｆ％θ、フ゛う欠］７り（Ｚｆ
Ｅ−一−焚舛理Figure 1 a % d is a process-order sectional view of an embodiment of the present invention, Figure 2 a - d is a process-order sectional view of a conventional example, and Figure 3 is a characteristic diagram showing the heat resistance of PMMA according to an example of the present invention. , FIG. 4 shows 0FPRso according to an embodiment of the present invention. FIG. 2 is a characteristic diagram showing the heat resistance of. 1... Semiconductor substrate, 2... Resist pattern, 3... Plasma containing F or CI, 4
...Metal, 6...Metal electrode, 6...
...o2 plasma. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure A~--CFq9%θ2 BrazufutsukeiB---Dt
7-Rasuma Masuri C---Jake (Seijyo Processing Haruka/￥c6c) Kayu 4 Figure D---C2Hα3/, f%θ, [missing] 7ri (Zf
E-1-Takimasuri
Claims (2)
に、同レジストの膜減り量が所定量以内の短時間のあい
だ、ＦまたはＣｌを含むプラズマを照射した後、金属を
蒸着し、ついで前記レジストと共にリフトオフする工程
をそなえた金属パターン形成方法。(1) A resist pattern of a predetermined shape formed on a substrate is irradiated with plasma containing F or Cl for a short period of time until the amount of film loss of the resist is within a predetermined amount, and then a metal is vapor-deposited, and then a metal is vapor-deposited. A metal pattern forming method that includes a lift-off process along with resist.
る特許請求の範囲第１項に記載の金属パターン形成方法
。(2) The metal pattern forming method according to claim 1, wherein the amount of resist film reduction is controlled within 0.1 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17796285A JPS6237928A (en) | 1985-08-13 | 1985-08-13 | Metallic pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17796285A JPS6237928A (en) | 1985-08-13 | 1985-08-13 | Metallic pattern forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6237928A true JPS6237928A (en) | 1987-02-18 |
Family
ID=16040119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17796285A Pending JPS6237928A (en) | 1985-08-13 | 1985-08-13 | Metallic pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237928A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007214219A (en) * | 2006-02-08 | 2007-08-23 | Hitachi Ltd | Semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051257A (en) * | 1973-09-05 | 1975-05-08 | ||
| JPS53148279A (en) * | 1977-05-31 | 1978-12-23 | Fujitsu Ltd | Production of semiconductor device |
| JPS5532095A (en) * | 1978-08-24 | 1980-03-06 | Ibm | Stabilizing resist image |
| JPS55158630A (en) * | 1979-05-29 | 1980-12-10 | Ibm | Method of lifting off metallic layer formation |
| JPS5655055A (en) * | 1979-10-12 | 1981-05-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6060725A (en) * | 1983-09-14 | 1985-04-08 | Matsushita Electronics Corp | Forming method of pattern |
-
1985
- 1985-08-13 JP JP17796285A patent/JPS6237928A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051257A (en) * | 1973-09-05 | 1975-05-08 | ||
| JPS53148279A (en) * | 1977-05-31 | 1978-12-23 | Fujitsu Ltd | Production of semiconductor device |
| JPS5532095A (en) * | 1978-08-24 | 1980-03-06 | Ibm | Stabilizing resist image |
| JPS55158630A (en) * | 1979-05-29 | 1980-12-10 | Ibm | Method of lifting off metallic layer formation |
| JPS5655055A (en) * | 1979-10-12 | 1981-05-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6060725A (en) * | 1983-09-14 | 1985-04-08 | Matsushita Electronics Corp | Forming method of pattern |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007214219A (en) * | 2006-02-08 | 2007-08-23 | Hitachi Ltd | Semiconductor device |
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