JPS6238858B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and in particular to a method for integrating a programmable logic array (PLA) section consisting of an AND array and an OR array and peripheral circuits including logic circuits on the same semiconductor chip. The present invention relates to a semiconductor monolithic integrated circuit device.

An integrated logic device called a programmable logic array (PLA), which consists of an AND array and an OR array and whose logic can be easily changed according to the logic definition, is used as a device to realize arbitrary logic functions. There is. Examples of implementation of this device are shown in FIGS. 1 to 3. As an example, consider the logic given by the following equation (1).

In order to realize the logic of equation (1) using PLA, the first step is
As shown in the figure, input in AND array 1
Column lines X1, X2, X3, corresponding to x1, x2, x3, x4,
Lines Z1 to Z10 corresponding to outputs z1 to z10 with X4 vertically
Place next to it. Column lines 1-4 are similarly arranged through inverting circuits I1-I4 to obtain inverted inputs 1-4 of inputs x1-x4. Output line Z1~Z10
are connected to the power supply line Vcc through load resistors R1 to R10, respectively.
are commonly connected. Then, the intersections of the row lines and column lines are connected by diodes according to the logic of equation (1). In this case, for example, the column lines as input lines are constructed from a first layer wiring made of a polycrystalline silicon layer provided on a silicon chip, and the row lines as output lines are formed on top of the first layer wiring made of a polycrystalline silicon layer provided on a silicon chip. The second layer wiring is configured. In the silicon layer of the first layer wiring, PN junction diodes are formed in advance at all intersections of matrix lines, and according to the logic function,
diodes formed in the column lines at the intersections of the matrix lines;
The AND array 1 is constructed by connecting the row lines to the upper aluminum wiring layer by providing through holes in the insulating layer.

Next, in the OR array 2, the row lines Z1 to Z10 corresponding to the outputs z1 to z10 of the AND array 1 are used as row lines, and the outputs of the OR array 2 are used as row lines.
Column lines Y1 to Y5 are provided as y1 to y5 via inverting circuits I1' to I5'. And similar to AND array 1 (1)
The matrix lines are connected by diodes at predetermined intersections of the matrix lines according to the formula. In this case as well, the row line Z1~
Z10 is the second layer wiring aluminum wiring, and the matrix line is connected through the diode formed at the intersection of the matrix lines of the column lines Y1 to Y5, which is the silicon layer of the first layer wiring, and the through hole of the insulating layer. will be connected. Figure 2 shows how many logical functions can generally be easily realized using PLA.
In FIG. 2, in addition to the AND array and OR array shown in FIG. 1, an input buffer group 11 and an output buffer group 12 are added to form one integrated chip. The number of inputs x of the AND array is n,
If the number of outputs z is P and the number of outputs y of the OR array is m, then according to the logic device in Fig. 2, Any combinatorial logic can be realized within the range of .

FIG. 3 shows an example in which a part of the output buffer group in FIG. 2 is replaced with a flip-flop group 21, and the output 22 of the flip-flop group is returned to a part of the input buffer group 23, so that a circuit can be constructed sequentially. All such circuits are integrated into monolithic ICs on the same semiconductor chip.

By the way, in general, as the chip area of an integrated circuit device increases, the yield decreases, so it is desirable to have a configuration that reduces the chip area as much as possible, and it is also necessary to reduce the chip area of the devices shown in FIGS. 1 to 3 above. There is.

An object of the present invention is to provide a monolithic integrated circuit device constructed with a smaller chip area.

In other words, in order to realize the logic of equation (2) above, the conventional device requires an AND array with P rows and n columns and an OR array with P rows and m columns, so the total number is P(m+n). Requires multiple diodes. An object of the present invention is to provide a device in which the number of diodes is reduced to a number sufficiently smaller than P(m+n), thereby reducing the required chip area.

The present invention has a product term section to which n-bit input signals consisting of x1... In an integrated circuit device including a programmable logic array having a sum term part from which an m-bit output signal consisting of y1...ym is taken out in parallel from an output line on the other side, one of the diodes arranged in the sum term part It is characterized in that the output bits in the product term section are rearranged so that diodes connected to the same output line are continuous. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 has the same logical function as the above-mentioned FIG.
A first embodiment will be described in which the function expressed by equation (1) is realized in accordance with the purpose of the present invention. In other words, in FIG. 4, the AND array 31 replaces the rows in FIG. Only the area of PLA is reduced. Therefore, only two columns of OR array 32 are sufficient, and the number of diodes is compared to 130 in the case of Figure 1.
Only 100 pieces are required, which is a huge advantage.

A second embodiment is shown in FIG. 5. In this figure, the AND array 41 has Z5=x1x2
11 because the line 43 that realizes is created duplicated.
row, but because of this the disjunction array 4
2, only one row is sufficient. The number of diodes is only 99, compared to 130 in the case of Figure 1.

A third embodiment is shown in FIG. This is based on the input x4 in the OR array 51 based on FIG.
(52) is given from the opposite side to x1, x2, and x3. This reduces the number of diodes to 77. As can be seen from the above three embodiments, in the present invention, the wiring pattern of the row lines Z1 to Z10 in the second layer is changed, and therefore the through-hole position of the diode in the first layer wiring corresponds to the intersection of the matrix lines. (First,
Logic functions are realized with a small chip area by changing the openings in the insulating layer between the two wiring layers. Therefore, after the chip is completed, it is difficult for the user to construct an integrated device (referred to as a field programmable logic array) that realizes an arbitrary logic function according to the logic definition. However, for the output buffer group shown in FIG. 2 12 or FIG. 3 24 and the flip-flop group shown in FIG. If the intention is to increase the versatility of the integrated chip by determining the wiring pattern for connecting these wires, the wiring pattern will have to be changed in any case, so it is possible to change the wiring pattern within the array according to the present invention. becomes. In particular, as shown in FIG. 7, the input buffer group 61,
By repeatedly creating a master pattern 64 that can form an AND array 62, an OR array 63, an output buffer group, and a flip-flop group as one block 65, it is possible to realize a large-scale integrated logic device. In this case, the wiring pattern between blocks must be changed depending on the intended logic, so it is clear that the gist of the present invention can be put to good use.

As described above, the present invention provides a configuration in which an integrated device including an AND array and an OR array can be realized in a smaller area than before.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an example of a conventionally used AND array and OR array, Figure 2 is a general-purpose combinatorial logic device including a conventionally used AND array and OR array, and Figure 3 is a conventional circuit diagram. A general-purpose sequential logic device including an AND array and an OR array used, FIG. 4, FIG. 5, and FIG. 6 each show a logic device showing an embodiment of the present invention, and FIG. This is an example of a logical device being utilized. In the figure, 31, 41, and 51 are AND arrays, 32, 42, and 52 are OR arrays, X and Y are column lines, Z is a row line, x is an input, and y is an output, respectively.

Claims (1)

[Claims] 1 A product term section to which n-bit input signals are applied in parallel and outputs an l-bit AND signal in parallel; A programmable logic array has a sum term section that outputs OR signals of bits in parallel, and connects the intersections of the matrix lines of the sum term section together, and omit the matrix lines in the remaining area. An integrated circuit device comprising: