JPS6239064A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively decrease the space between an emitter and a base and the base resistance to improve the frequency characteristics, by interposing only an insulating film between a silicon film on the emitter region and a metal electrode film on the base region. CONSTITUTION:A P<-> type silicon substrate 1 is provided with an N<+> type collector buried layer 2, an N<-> type layer 3, a P-type layer 4, an isolation oxide film 102, an N<+> type diffused layer 8, a polysilicon film 600, an oxide film 202 and an oxide film 105. An N<+> type impurity is introduced into the film 600, a metal silicide film 701 is formed and a P-type impurity ion implanted layer is formed and annealed, whereby an emitter region 7 is formed in a self- aligning manner and an external base region 54 is formed to have a resistance lower than that of an active base region 6. An oxide film 107 is provided on N<+> type polysilicon films 603 and 604 containing the metal silicide film while an oxide film 108 is provided on the region 54. The oxide film 108 is removed and oxide films 203 are formed on the side walls of the film 608. Finally, a base electrode wiring layer 9 and an emitter electrode wiring layer 11 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming a polarization lead-out portion of a base in a bipolar semiconductor integrated circuit device.

[Conventional technology]

In general, transistors in a bipolar semiconductor integrated circuit device are formed in electrically independent islands by methods such as pn junction assembly, oxidation junction assembly using selective digitization technology, or 8-fold diffusion.

Here, a method for forming an npn l-transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, further pnp)-
This can also be applied to transistors.

@ Figures 5A to 5E are diagrams showing the cross-sectional structure of a semiconductor device at main process steps (ζ) according to a conventional manufacturing method.Hereinafter, with reference to Figures 5A to 5E, the conventional manufacturing method will be briefly explained. Explain.

In FIG. 5A, a highly impurity-concentrated n-type (n+-type) layer 2 is selectively formed on a p-type (p-type) silicon substrate 1 with a low impurity magnetism to serve as a collector-embedding layer. Next, an n-type epitaxial layer 8 is formed on the silicon substrate 1 and the n-medium layer 2.

In Figure 6B, underlay oxidation@101 and nitridation [20
1 is formed in a predetermined area on the n-skin 8. Nitriding [20
At the same time as p-type@4 annealing for channel cutting using 1 as a mask, a thick isolation oxide film 102 is formed by selective oxidation using the nitride film 201 as a cester.

In FIG. 6C, first, the oxidation gland 201 used as a mask for selective oxidation is removed together with the underlying oxide film 101. Next, an oxide film 108 for protecting ion implantation is formed again, and a p-type medium layer 6, which will become an external base layer, is formed using a photoresist layer (the photoresist layer is not shown) as a mask. Furthermore, the above photoresist section is removed, and a photoresist [801] is formed again in a predetermined shape, and using this O as a mask, p
Type j-6 is formed by ion implantation.

In FIG. 5v, the photoresist 1i 1801 is removed and then a passivation film 401, generally the adjacent glass ()'5 (J), is deposited. A heat treatment is performed that combines the annealing of the base ion press-fit skins 6 and 6 and the baking of the '5Gfi401.
and active base layer 61 is formed. Next, an emitter electrode contact hole 70 and a collector electrode contact hole 80 are formed in a predetermined area of the PSG tear 401, and through these contact holes 70. Medium size, Ill 7
Then, an n medium-sized layer 8 which is to serve as a collector electrode extraction device is formed.

In FIG. 5E, each ion implantation layer is annealed seven times to complete the external base layer 52 and active base layer 62, and to form the emitter layer 71 and the collector electrode JfII 81. Metal silicide tears 601 are formed in each of the openings 50, 70 and 80 to prevent electrode penetration (for example, to prevent reaction between A7 and 51). For this metal silicide teardrop 501, base silicide (Ft-bi), palladium silicide (Pd-Sl), or the like is used. A base IIE electrode wiring 9. is formed using a low resistance metal such as aluminum on the metal silicide layer 501. Emitter electrode wiring 10 and collector electrode wiring 11 are formed.

[Problem that the invention seeks to solve]

Incidentally, the frequency characteristics of a transistor depend on the base-collector configuration, base resistance, and the like.

Therefore, in order to improve the frequency characteristics of the transistor, it is necessary to reduce these. The p+ pear-shaped outer base 1-52 in the conventional structure described above is provided to reduce base resistance.

However, this external base layer 52 has the disadvantage of increasing base-collector capacitance.

FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. The base resistance is the distance 14' between the emitter J-71 and the base electrode extraction hole 50 shown in Figure 6E.
Ordained L L't. In the conventional device, the distance is the sum of the same temperature of the base electrode wiring 9 and the emitter electrode wiring 10 and the protrusion of each of the electrode wirings 9 and 10 from the opening 50.70. Therefore, even if the photoetching accuracy is increased and the yittm wiring spacing is reduced, the above-mentioned protrusion will inevitably remain. Also, the 6th
The base region between the emitter layer 71 and the oxidation section boundary A shown in the figure is a non-active region, increasing the base-collector valley. In order to eliminate this non-active region, there is a method of forming a walled emitter structure in which the emitter layer 71 is in contact with the split layer oxidation gland. However, this method also suffers from severe drawbacks.

7A to 7C are views showing a part of the cross section taken along the line XX in FIG. 6. FIG. Hereinafter, with reference to FIGS. 7A to 7C, problems of the conventional walled emitter structure i.
Let me explain in detail.

Figure 7A shows the photoresist gland 80 for base formation.
1 as a mask and p as an impurity boron implanted. Next, it is necessary to remove the oxide film 108 on the emitter region 7 to form a contact hole. However, in this walled emitter structure,
As shown in FIG. 7B, boundary A of the divided ill 102 is overetched during oxidation gland removal, and the emitter region becomes deeper as shown at B in FIG. 7C. As a result, there is a large risk that the controllability of the current amplification factor will deteriorate and furthermore, a short circuit will occur between the emitter and the collector at the portion B shown in FIG. 7C.

Furthermore, as a method of reducing base resistance, a double base structure as shown in FIG. 8 is often used. However, the conventional method has the disadvantage that the base area increases due to the extraction of the base electrode, which leads to an increase in base-collector capacitance.

In addition, in the conventional manufacturing method, the emitter base junction is made deeper than the surface of the external base region, which has the disadvantage that the current amplification factor has a thick dependence on viL&. There is a problem in that current is collected in the field ml (emitter external base region, etc.) due to recombination, etc., and the control of the current amplification factor deteriorates.

Therefore, the purpose of this invention is to eliminate the above-mentioned drawbacks, reduce the base resistance and base-collector electrode wiring, reduce the current dependence of the current amplification factor in the low tUt range, and furthermore create a semiconductor with good frequency characteristics. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain high performance.

[Means for solving problems]

The method for manufacturing a semiconductor according to the present invention is to form a silicon group (either single crystal amorphous or polycrystalline) having impurity diffusion for forming an emitter region on a semiconductor i-plate region which becomes an emitter region, and form a base region. A part of the emitter region is formed by ion implantation through this silicon group, and then an emitter region is formed in the base region in a self-aligned manner using this silicon group.

Furthermore, an insulating film is formed in a self-aligned manner between the polysilicon film on the emitter region and the base electrode lead-out region to insulate the base-emitter electrode, and furthermore, the base electrode lead-out region is formed in a self-aligned manner. At this time, the emitter-base junction is formed to be shallower than the external base hollow region: tc plane and at a depth in the direction of the base electrode extraction portion.

[For fμ]

Since the emitter region is formed in the base region in a self-aligned manner, the emitter region is diffused, and a patterning mask such as a polysilicon group connected to the metal electrode is used to form the minimum amount around the emitter silicon tear in a self-aligned manner. A base 11Ic pole extraction region is formed.

Moreover, since only an insulating film is interposed between the silicon film on the emitter region and the metal wiring on the base region, the emitter-base distance becomes small and becomes approximately the thickness of this insulating film.

Furthermore, since the emitter region is formed by diffusing impurities from the polysilicon film, which serve as impurity diffusion, into the region that is to become the emitter region, there is no need to form a contact hole for ion implantation when forming the emitter region. . Therefore, there is no need to remove the oxide film on the emitter region, and over-etching at the isolation oxide film boundary does not occur. become.

Furthermore, the emitter base junction is made shallower than the surface of the external base region, so there is no absorption due to recombination, and the current dependence of the current amplification factor in the low current region is reduced.

[Examples of practical examples of the invention]

FIGS. 18 to 1J are cross-sectional views at main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained with reference to FIGS. 1A to 1J.

Referring to FIG. 1A, an n-type collector is buried in a predetermined region of a p-type silicon substrate 1 62. n-type epitaxial 1-3. P type m4 for channel cutting. Separate oxidation &1
02. An n+ type diffusion no. 8 is formed which becomes a collector electrode extraction region. The formation of each region is shown in FIGS. 6A and 5.
This is done using a method similar to the conventional method shown in FIG.

Next, as shown in FIG. 5B, the underlying oxide film 101 and nitride film 201 are removed, and a silicon layer, preferably a polysilicon layer 600. A molded film 202 and an oxide film 104 are formed in this order on the surface of the semi-integrated substrate 1.

Next, using the resist group 808 having a predetermined pattern shape as a mask, the multilayer film consisting of the polysilicon group 600, the m film 202, and the oxide film 104 is etched. By this patterning, oxidation lines 104.
The violet 202° polysilicon group 600 is left behind.

See Figure 1B. Using the resist image 808 used for patterning the multilayer film in the above process as a mask, only the side walls of the oxide film 104 included in the multilayer film are side etched. As a result, the oxide film 104 becomes polysilicon! 60
0 and retreats inward from the nitride film 202.

In FIG. 1C, selective oxidation is performed using the nitride film 202 as a mask to form an oxide film 105 in a predetermined region on the surface of the semiconductor substrate.

In FIG. 1V, etching is performed using the oxide film 104 as a mask to pattern the polysilicon H600 underlying the nitride a5@202 and the nitride layer 202, and furthermore, the layer thickness of the silicon substrate (n layer 8) is determined in advance. is removed by etching, and the portion that will become the base electrode is cut into four. This is to reduce the current dependence of the current amplification factor by forming the emitter junction (junction between the active base region and the emitter region) at the same depth as the base electrode extraction layer. That is, 9 in the recombination lζ
To eliminate absorption of 1t current and to reliably control current amplification factor even in a low current region.

See Figure 1E. On the night after the oxide film 104 was removed, selective oxidation using the nitride film 202 as a mask caused oxidation i 1
06 is formed on the surface of the semiconductor substrate between the polysilicon group 600 and the oxide film 105.

At this time, selective oxidation is performed on the thinned polysilicon group 600.
This is done to such an extent that not only the n-type semiconductor region 3 thereunder is also slightly oxidized. Oxide film 106 is polysilicon film 6
Cover the side wall of 00.

In FIG. 1F, -1 first, the image 202 is removed.

Next, polysilicon y 6 is made using the eyes 106 as a mask.
By adding an n+ type impurity to 00, an impurity-containing polysilicon group 601 is formed. This makes polysilicon film 60
1 serves as an impurity diffusion source for forming an emitter region. Next, metal silicide group 701 was added for the purpose of reducing emitter resistance.
is formed in a self-consistent manner. For example, titanium silicide (
It is well known that Ti (512) is formed in a self-aligned manner only in the portion in contact with the silicon surface, and that the =m process can be performed.

First (in figure J, after the oxide film 106 is removed, p
Type impurities are ion-implanted to form an ion-implanted layer 52',
51, 52.58 are formed. At this time, the oxide film 10
The removed portion 6 becomes the n-type semiconductor region or the external base layer. On the other hand, oxide film 106 is left to separate the base region and collector region. Therefore, the oxide film 105
The oxide film 106 is formed as thick as 1 μm in the selective oxidation shown in FIG. 1C, and as wide as 200 to 100 nm in the selective oxidation shown in FIG. 1B and F. In addition, the 1) layers 52' and 52 formed by ion implantation into the collector electrode extraction region have an almost negligible amount of impurity due to the n+ diffusion @ 8 for collector electrode extraction, and have almost no effect on the collector electrode extraction diffusion layer 8. does not affect In addition, the ion-implanted region that should become the active base layer under polysilicon@602 (polysilicon fi601 implanted with P-type impurities) is ion-implanted with p-type impurities through polysilicon y602, so Area 6 that should be the base layer
It is formed shallower than 8.

In Figure 1)i, the annealing of the p-type lower impurity ion implantation layer and the diffusion of the n0-type impurity from the polysilicon group 602 into the silicon substrate 8 are performed simultaneously. As a result, emitter region 7 is formed in a self-aligned manner, and external base region 54 is formed slightly deeper and with lower resistance than active base region 6. Next low temperature (800'C ~
A thick oxide film 107 is formed on the n+ type polysilicon layer 608 and 604 including the metal silicide film, and a thick oxide film 108 is formed on the Ijp+ type silicon substrate 54. utilizes the well-known fact that enhanced oxidation occurs at low temperatures in silicon and polysilicon filled with n-type impurities or containing arsenic or the like at high acidity.

In FIG. 11, oxides @107,10 formed on polysilicon l5oa and soa containing metal silicide
At step 8, anisotropic etching (KIE) is performed to remove the thin oxide film 108 on the extrinsic base region 54. Here, as a method of preventing short-circuiting of the bases llk, & to the emitters JJ 7, a plating layer 208 is deposited on the entire surface shown in FIG. 1B, and the side walls of the polysilicon group 608 are etched by anisotropic etching. After leaving Ninomiya Chemical Company 208 behind, he once again asked RIE (K active I onb).
The oxide film 108 is formed using the
There is a method of removing the 608% polysilicon wall and leaving an oxidized gland-golden layer on the polysilicon wall, and this state is shown in FIG.

In FIG. 1J, first, the thick oxide 11i 108 on the collector electrode extraction region 8 is removed. Next, selective etching is performed in a predetermined area to form an emitter core contact hole 70 (not shown in FIG. 1J) and a collector electrode contact hole 80. For example, a low resistance metal such as A7 (such as A7) may be used to make the base part of the base.
Emitter electrode arrangement h l O (not shown in Figure IJ)
and collector electrode arrangement 11 are formed, respectively. E
As seen from the IJ diagram, the emitter-base spacing is approximately equal to the oxide film 197 on the sidewall of the polysilicon layer 608 and the nitride film @
208, the base resistance is extremely small.

FIG. 2 is a plane pattern diagram of the transistor fabricated in one embodiment of the above-mentioned double-page spread, and corresponds to the plane pattern diagram of the conventional transistor shown in FIG. As shown in FIG. 2, the emitter electrode white edge 1
Since the polysilicon M 608 connected to 0 serves as a diffusion source for the emitter region 7, the emitter region 7 comes into contact with the Mangeki oxidation film 102 at the point in the figure. Furthermore, unlike the conventional method shown in FIG. 7, the emitter region 7 is formed in a self-aligned manner by diffusion of impurities from the polysilicon group 608, so that the base region is not partially oxidized.
There is no overetching and narrowing in the vicinity of 102. That is, as shown in FIG. 8, emitter region 70 and active base region 6 are formed simultaneously through polysilicon group 608, so that they are substantially parallel and the base width is constant.

Therefore, the base area is significantly reduced due to the elimination of the protruding area between the emitter base and the pole, and the fact that the base and extraction area are formed in a self-aligned manner with the minimum area, and the base-collector condition is improved. reduced. Furthermore, as shown in FIG. 2, the base electrode wiring 9 is formed around the emitter region 7 on three sides, so it automatically forms a double base structure, without causing an increase in the base region. Base resistance is significantly reduced.

In addition, since the emitter junction is formed shallower than the surface of the external base region and at the same depth as the base electrode extraction I-, there is no absorption of current due to recombination at the interface, and the current flowing through the low flow region E is eliminated. The current dependence of the amplification factor is reduced.

As another example, as shown in Figure #4, instead of performing the n-type impurity diffusion for forming the collector electrode extraction region, in step 1 shown in Figure 1G, the resist group 8 is
04 as a mask, after removing the oxidized tear 106 in the base region, p-type impurity is selectively implanted and annealing is performed. As a result, the n-type impurity is diffused from the polysilicon group 604 into which the n-type impurity has been implanted, and an electrode lead layer can be formed.

Needless to say, the present invention can also be used for manufacturing pnp (pnp) transistors.

〔Effect of the invention〕

As described above, according to the present invention, since only an insulating film is interposed between the silicon film on the emitter region and the metal electrode on the base region, the distance between the emitter and base can be effectively reduced, and the distance between the emitter and base can be effectively reduced. As a result, the base resistance is reduced and the frequency characteristics of the semiconductor device are improved.

In addition, the emitter region is formed by diffusing impurities for forming the emitter region into the value range that is to become the emitter region using the polysilicon family as a diffusion source, and at the same time, the impurity for forming the base head is further diffused into the semiconductor substrate. Since the base region is completed by using the emitter region, the separation region boundary is not overetched, and the emitter region and the base region can be brought into contact with the nitride region in a substantially parallel state.

Furthermore, since the base tilt pole extraction region is formed with the minimum area in self-alignment with the pattern for forming the emitter region, the inactive base region is significantly reduced.
Based on the pattern dimensions of the resist image 808 shown in the figure, the polysilicon group 60 forming the emitter layer is formed by side etching and the so-called bird's beak biting during selective oxidation.
Since the pattern size of 8 is 178 or less, it is possible to easily realize an emitter region with a submicron width.

Furthermore, since the emitter junction is formed shallower than the surface of the external base region and is on the same level as the base electrode extraction layer, the current dependence of the current amplification factor is reduced. In the manner described above, it is possible to manufacture a semiconductor integrated device with improved frequency characteristics.

[Brief explanation of drawings]

FIGS. 18 to 1J are diagrams showing the main process steps of the manufacturing method according to the embodiment of the present invention. FIG. 2 is a plan pattern diagram of a transistor manufactured by the method of the present invention. FIG. 8 is a schematic cross-sectional view of the semiconductor device according to the present invention near the isolation region boundary. FIG. 4 is a cross-sectional structural diagram of a method of manufacturing a semiconductor device according to another embodiment of the present invention. Figure 58 to gg5i
The figure is a cross-sectional view showing the state of a semiconductor device at the main process steps of a conventional manufacturing method. FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. FIGS. 78 to 7C are schematic cross-sectional views of the vicinity of the isolation oxide film when the emitter layer is formed in contact with the isolation oxide film by the conventional method. Figure 8 shows a double
This is a plan pattern diagram of a transistor with a base structure. In the figure, 1 is a p-5 silicon substrate, and 2 is a p-5 silicon substrate. + type collector embedded fat, 8 is n- type epitaxial addition,
5 is a region to be the external base 1=, 52°54 is an external base region, 6.62 is an active base region, 7 and 71 are emitter head mounting regions, 8 and 81 are collector electrode extraction regions, and 9 is a base l! Polar wiring, 10 is emitter electrode wiring, 11 is collector electrical wiring, 50 is a contact hole for base Xtljt, 70 is a contact hole for emitter electrode, 80 is a contact hole for collector electrode, 102 is an isolation oxide film, 108, 1
04゜105.106, 107, 108 are oxide films, 20
1゜202.208 is a plating film, 808, 104 is a photoresist i, 401 is a passivation group, 600.6
01, 602, 608, and 604 are polysilicon. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device formed on a semiconductor substrate of a first conductivity type and comprising an emitter region, a collector region, and a base region, wherein the semiconductor device is electrically connected to an adjacent semiconductor device by a separation region. a first step of forming a multilayer film in which a silicon film, a nitride film, and an oxide film are deposited in a predetermined region on the surface of the semiconductor substrate; a second step of side-etching only the oxide film to be retreated inward from the nitride film and the silicon film, and performing selective oxidation using the nitride film as a mask to form a predetermined area on the semiconductor substrate. a third step of forming a first oxide film, and selectively anisotropically forming a predetermined depth region of the nitride film, the silicon film, and the semiconductor substrate using the side-etched oxide film as a mask; a fourth step of performing selective oxidation using the selectively etched nitride film as a mask to remove the surface of the semiconductor substrate between the silicon film and the first oxide film; a fifth step of forming a second oxide film thereon; a sixth step of introducing impurities of the first conductivity type into the silicon film using the second oxide film as a mask; a seventh step of converting the upper part into a metal silicide film; an eighth step of removing the second oxide film on the region of the base region that will become the electrode extraction portion; a ninth step of introducing an impurity of a second conductivity type; performing a heat treatment on the semiconductor substrate to diffuse the impurity of the first conductivity type from the silicon film into a region to become the emitter region; and at the same time completing the base region; performing a low-temperature oxidation treatment on the semiconductor substrate to form a silicon film on the sidewalls and top surface of the silicon film including the metal silicide film connected to the emitter region; forming an emitter electrode through an opening penetrating the third oxide film formed in a predetermined region on the silicon film, and forming an emitter electrode on the semiconductor substrate; a twelfth step of providing electrode wirings serving as a base electrode and a collector electrode on predetermined regions of the semiconductor device. (2) Between the eleventh step and the twelfth step, a nitride film is further formed on the sidewall of the third oxide film formed on the silicon film including the metal silicide film connected to the emitter region. A method for manufacturing a semiconductor device according to claim 1, comprising the step of: (3) In the fourth step, the predetermined depth of the semiconductor substrate that is selectively removed is a depth such that the emitter base junction is shallower than the surface of the external base region. A method for manufacturing a semiconductor device according to claim 1 or 2.