JPS6239330U - - Google Patents

Info

Publication number
JPS6239330U
JPS6239330U JP13217285U JP13217285U JPS6239330U JP S6239330 U JPS6239330 U JP S6239330U JP 13217285 U JP13217285 U JP 13217285U JP 13217285 U JP13217285 U JP 13217285U JP S6239330 U JPS6239330 U JP S6239330U
Authority
JP
Japan
Prior art keywords
diode
varactor diode
voltage applied
utility
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13217285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13217285U priority Critical patent/JPS6239330U/ja
Publication of JPS6239330U publication Critical patent/JPS6239330U/ja
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例の回路図、第2図は通
常のトラツキング特性図、第3図は本考案の動作
の説明図、第4図はスーパーヘテロダイン受信機
の一般的なブロツク図、第5図は従来の共振回路
、第6図は本考案の他の実施例の回路図、第7図
は上記実施例のトラツキング特性図である。 D,D……バラクタダイオード、C……
付加コンデンサ、D……ダイオード。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a normal tracking characteristic diagram, Fig. 3 is an explanatory diagram of the operation of the present invention, Fig. 4 is a general block diagram of a superheterodyne receiver, FIG. 5 is a conventional resonant circuit, FIG. 6 is a circuit diagram of another embodiment of the present invention, and FIG. 7 is a tracking characteristic diagram of the above embodiment. D 1 , D 2 ... Varactor diode, C 0 ...
Additional capacitor, D 0 ... diode.

Claims (1)

【実用新案登録請求の範囲】 1 a 可変コンデンサとして第1のバラクタダ
イオードを用いた高周波同調回路。 b 可変コンデンサとして前記第1のバラクタ
ダイオードと同一特性の第2のバラクタダイオー
ドを用いた局部発振回路。 c 前記第1のバラクタダイオードに並列接続
した付加コンデンサとダイオードとの直列回路。 d 前記ダイオードの一端に加える制御電圧。 e 前記ダイオードの他端に加える基準電圧。 以上の各項目を具備することを特徴とするスー
パーヘテロダイン受信機。 (2) 付加コンデンサとダイオードとの直列回路
を並列に複数設けたことを特徴とする実用新案登
録請求の範囲第1項に記載のスーパーヘテロダイ
ン受信機。
[Claims for Utility Model Registration] 1 a. A high frequency tuning circuit using a first varactor diode as a variable capacitor. b. A local oscillation circuit using a second varactor diode having the same characteristics as the first varactor diode as a variable capacitor. c. A series circuit of a diode and an additional capacitor connected in parallel to the first varactor diode. d Control voltage applied to one end of the diode. e Reference voltage applied to the other end of the diode. A superheterodyne receiver comprising each of the above items. (2) The superheterodyne receiver according to claim 1 of the utility model registration, characterized in that a plurality of series circuits of additional capacitors and diodes are provided in parallel.
JP13217285U 1985-08-28 1985-08-28 Pending JPS6239330U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13217285U JPS6239330U (en) 1985-08-28 1985-08-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13217285U JPS6239330U (en) 1985-08-28 1985-08-28

Publications (1)

Publication Number Publication Date
JPS6239330U true JPS6239330U (en) 1987-03-09

Family

ID=31031308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13217285U Pending JPS6239330U (en) 1985-08-28 1985-08-28

Country Status (1)

Country Link
JP (1) JPS6239330U (en)

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