JPS6239538B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor integrated circuit formed on an epitaxial layer on a silicon substrate. The present invention relates to a method of forming a silicon oxide film to be formed on the isolation band region.

Generally, when manufacturing a semiconductor integrated circuit element by forming a semiconductor element such as a transistor in an epitaxial layer on a silicon substrate, a protective film such as a silicon oxide film is formed in addition to the electrode connection hole of the semiconductor element such as the transistor. After that, a conductive material such as aluminum (Al) for wiring is often formed on the silicon oxide film by vapor deposition or the like.

In such cases, a method is used in which a thick silicon oxide film is formed around and above the semiconductor element in order to reduce the parasitic capacitance between the silicon substrate and the Al wiring.

In addition, in order to prevent parasitic effects between the semiconductor elements such as the transistors, there is a method in which an impurity of a conductivity type opposite to that of the epitaxial layer is added between the semiconductor elements to form an isolation band region between the elements. It is used.

FIG. 1 is a cross-sectional view showing the formation region of a conventional bipolar integrated circuit, particularly a transistor, in which 1 is a P-type silicon (Si) substrate, and 2 is a substrate formed on the substrate in order to improve the withstand voltage between the collector and base of the transistor. 3 is a high-concentration n-type buried layer for the purpose of reducing the series resistance of the collector of the transistor, and the figure shows that impurities in the buried layer are ,
This figure shows the state of diffusion into the epitaxial layer during the process of forming the epitaxial layer. Further, 4 is a P-type base region of the above transistor, 5 is an N-type emitter region of the above transistor, 6A,
6B and 6C are thick silicon oxide films for reducing the parasitic capacitance between the substrate and the Al electrode formed on the silicon oxide film on the substrate and the junction capacitance on the sides of the diffusion region, and 7 is the epitaxial layer. This is a P-type element isolation band region having a conductivity type opposite to that of an epitaxial layer for electrically isolating elements such as transistors formed in large numbers in the semiconductor device.

Further, 8 is a silicon oxide film that protects the surface of the semiconductor element such as the transistor. Here the second
The figures up to FIG. 8 are cross-sectional views showing the steps up to the formation of a base region of a transistor in the conventional manufacturing process of a bipolar integrated circuit element, and the conventional manufacturing process will be sequentially explained using the above drawings.

As shown in FIG. 2, an n-type high-resistance epitaxial layer 2 is formed on a P-type silicon substrate 1 having a high concentration n-type buried layer 3, and a predetermined layer is formed on the epitaxial layer. A patterned silicon nitride film 9 is formed.

Here, the figure shows a state in which the impurities in the heavily doped n-type buried layer 3 formed on the substrate are somewhat diffused into the epitaxial layer as described above.

Further, in the figure, part A is a region where a separation band is to be formed to separate each element such as a transistor formed in the epitaxial layer, part B is a region where a base is to be formed of the transistor, and part C is a region where the collector electrode of the transistor is connected. This is the area where the section is planned to be formed.

Next, the above substrate was heated to approximately 1000°C to form a thick oxide film on a relatively flat surface to reduce parasitic capacitance.
Thermal oxidation is performed at a temperature of about 1 hour to form a silicon oxide layer 10 of about 7000A using the silicon nitride film 9 as a mask, and then the silicon oxide layer formed above is removed by etching, or by an etching method. A groove 10 is formed as shown in FIG.

The silicon substrate is thermally oxidized again at a temperature of about 1000 DEG C. for 2 hours to re-form a thick silicon oxide layer 11 of about 1.0 .mu.m where the silicon oxide layer 10 can be removed, as shown in FIG.

Generally, silicon nitride film 9 prevents the passage of oxygen, so that almost no silicon oxide film is formed under silicon nitride film 9. However, in order to reduce the parasitic capacitance that occurs between the surface of the transistor region and the Al electrode formed on the silicon oxide film on the surface and the junction capacitance on the side surface of the diffusion region such as the base, it is necessary to The silicon oxide layer 11 needs to be relatively thick at 1 μm or more, and the oxidation progresses in the lateral direction at the same time as the oxidation in the depth direction, and a thick silicon oxide layer 11 is also formed under the periphery of the silicon nitride film 9.

Normally, it is difficult to diffuse impurities through the thick silicon oxide layer 11, so the silicon nitride film 9 is deposited over a large area in advance in anticipation of the lateral spread of the thick silicon oxide layer 11.

Next, a photoresist film (not shown) is deposited on the area other than the region where the isolation zone is to be formed, and P-type impurity atoms are ion-implanted into the region where the isolation zone is to be formed at a high concentration as shown in FIG. A P-type layer 12 is formed.

Next, a photoresist film (not shown) is deposited on a portion of the transistor other than the area where the collector electrode is to be connected, and n-type impurity atoms are ion-implanted into the area where the collector electrode is to be connected, resulting in a high concentration of n-type impurity atoms as shown in FIG. A mold layer 13 is formed. One of the advantages of this method is that these photoresist films may have a rough pattern that covers the desired portions of the silicon nitride film 9, since the thick silicon oxide layer 11 acts as an ion implantation mask.

Next, the silicon substrate formed as above is
By heat treatment at 1100℃ for about 1 hour, the 6th
As shown in the figure, impurities in the highly concentrated P-type layer 12 formed by ion implantation are allowed to reach the lower P-type silicon substrate 1 from the epitaxial layer 2 to form an isolation zone region 14. do.

At the same time, through this heat treatment, the impurities in the highly concentrated n-type layer 13 previously formed by ion implantation are diffused into the buried layer 3 formed in the substrate, thereby forming the collector electrode connection region 15 of the transistor. do.

Furthermore, the silicon nitride film on the collector electrode connection region, the isolation zone region between elements, and the region where the base is to be formed may form an interface state in the underlying silicon substrate during operation, so the silicon nitride film should be removed once. Then, as shown in FIG. 7, a new silicon oxide film 16 with a thickness of about 500 Å is formed on that part as a surface protection film.

Next, a photoresist film 17 is deposited on a portion other than the region where the base is to be formed, and then P-type impurity atoms are ion-implanted into the region where the base is to be formed to form a highly concentrated P-type layer 18 necessary for forming the base region. do.

Furthermore, after removing the photoresist film 17,
Highly concentrated P-type layer 18 formed by the above ion implantation by heat treatment at a temperature of about 1000°C for several minutes
The impurities contained therein are diffused into the epitaxial layer to a predetermined depth necessary for forming the base region, thereby forming the base region 19 as shown in FIG.

In this way, even the base region of the transistor of the bipolar integrated circuit element is formed, and the silicon oxide film 16 on the base region of the collector electrode connection region of the transistor and the isolation band region between the elements protects the surface. The thickness is only about 500 Å because of the purpose of the film, and even if an oxide film is deposited by vapor phase growth, the thickness is at most 0.4 to 0.5 μm. If formed, a parasitic capacitance will be generated between the base and the Al electrode, which has the disadvantage of deteriorating the characteristics of the device.

In addition, in order to eliminate the above-mentioned drawbacks, an even longer heat treatment process is required to form a thicker silicon oxide film on the semiconductor element formation region and the isolation zone region. In the meantime, impurities in the n-type high concentration buried layer formed on the substrate diffuse into the epitaxial layer, and the collector,
There is also the problem that the withstand voltage between the bases decreases.

Another drawback was that the silicon oxide film formed on the isolation band region and between the device and the isolation band region rose above the surface on which the device was formed.

By the way, if a thick silicon oxide layer is provided on the semiconductor element formation region, there is a problem that it becomes difficult to open each connection electrode window in a later step. On the other hand, since the element isolation region occupies a relatively large area, the generation of parasitic capacitance on the element isolation region has a large effect on element characteristics.

The present invention aims to provide a novel method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks by suppressing the influence of parasitic capacitance in the isolation region between elements, and is characterized by the following steps.

First, a silicon nitride film in a predetermined pattern is formed on a region of a silicon epitaxial layer formed on a silicon substrate where a semiconductor element is to be formed and a region where an isolation band having a conductivity type opposite to that of the epitaxial layer is to be formed. After forming a silicon oxide film on the surface of the remaining epitaxial layer using the silicon nitride film as a mask, only the silicon nitride film on the region where the isolation band is to be formed is removed, and the silicon oxide film and the remaining silicon are removed. In a heat treatment process in which a predetermined impurity is added to the region where the isolation band is to be formed using the nitride film as a mask and the impurity is diffused into the epitaxial layer, the silicon nitride film removed region including the isolation band region is A silicon oxide film is formed on the surface.

The present invention eliminates the drawbacks of the prior art by using a method for manufacturing a semiconductor device characterized by the steps described above.

An embodiment of the present invention will be described in detail below with reference to the drawings.

9 to 15 are cross-sectional views showing embodiments of the bipolar integrated circuit according to the present invention up to the formation of the collector electrode connection region and the isolation zone region, and as shown in FIG. 9, for example, as described above. ,
An n-type high-resistance epitaxial layer 33 is formed on a P-type silicon substrate 32 having an n-type high concentration buried layer 31 .

Thereafter, patterned silicon nitride films 34A, 34B, and 34C are formed on the region E where the isolation band is to be formed, the region F where the base is to be formed, and the region G where the collector electrode is to be connected, respectively, of the epitaxial layer.

Thereafter, as shown in FIG. 10, using the patterned silicon nitride film as a mask, the surface of the remaining epitaxial layer is etched to a depth of about 5,000 to 6,000 Å to determine the position between each region. The etching method at this time may be a method using immersion in a mixed solution of hydrofluoric acid-nitric acid-acetic acid, or a method using plasma etching.

After that, the above substrate was heated at about 1000℃ for about 1 hour,
A silicon oxide film 35 having a thickness of about 500 to 6000 Å is formed on the etched area by thermal oxidation to define a diffusion impurity deposition region.

Next, after forming a photoresist film at a location other than the silicon nitride film 34A patterned on the element isolation region, the silicon nitride film 34A is
Only the remaining parts are removed by plasma etching.

Next, the surface of the epitaxial layer exposed in the removed portion of the silicon nitride film 34A is similarly removed by plasma etching to a depth of about 3000 Å. This step is not necessarily necessary for carrying out the present invention, and in that case, FIG. 12 shows a state in which the oxide film 35, which will be described below, is removed by etching the silicon on the isolation zone region.

Here, 36 is the surface of the epitaxial layer etched by the plasma etching. By etching the surface of the epitaxial layer in the device isolation region in this way, the silicon oxide film that will be formed on the device isolation region in a later process will not swell in this area, and the surface of the integrated circuit device formed will be flat. I will be in charge.

Next, with a photoresist film formed in areas other than the area where the device isolation band is to be formed, boron atoms, which are P-type impurities, are ion-implanted to form a highly concentrated P-type layer 37 as shown in FIG. . This step may be performed by a normal impurity diffusion process, in which case it is not necessary to form a new diffusion mask film.
Furthermore, a photoresist film is deposited on a portion other than the area where the patterned silicon nitride film 34C is intended to be connected to the collector electrode, and then n-type, for example, phosphorus atoms are ion-implanted through the silicon nitride film 34C to form a highly concentrated n-type film. Form layer 38.

Next, after removing the photoresist film, the previously formed silicon oxide film 35 is removed by etching with hydrofluoric acid.

In this case, the hydrofluoric acid hardly etches the silicon substrate, and the silicon oxide film 35 is etched.

The state formed in this manner is shown in FIG. After that, the above-mentioned substrate formed in this way,
The above P is heated at a temperature of about 1100℃ for about 2 hours.
As shown in FIG. 15, boron atoms in the type high concentration layer 37 are allowed to reach the P type silicon substrate 32 to form an isolation zone region 39 between elements.

At the same time, through this heat treatment, the phosphorus atoms in the previously formed high concentration n-type layer 38 are diffused into the buried layer 31 formed in the substrate 32, thereby forming the collector electrode connection region 40.

At the same time, a thick silicon oxide film 41A is also formed on the isolation zone region from which the silicon nitride film 34A has been removed by this heat treatment, and between each region, that is, between the region where the collector electrode is to be connected and the region where the base is to be formed. A thick silicon oxide film 41B is also formed.

As described above, according to the method of the present invention, the formation of a thick surface oxide film between each diffusion region other than each electrode connection window forming portion of the element and the impurity diffusion process can be performed simultaneously. There is no need to anticipate the lateral spread of the chip in advance, allowing for higher integration.At the same time, a thick surface oxide film is formed on the isolation zone area, which eliminates the need for isolation zones that occupy a large area within the chip. Deterioration of device characteristics due to parasitic capacitance on the region can be significantly reduced.

In addition, the thick silicon oxide film formed around the transistor element and the thick silicon oxide film formed on the isolation band region become flat, and no step is formed in the aluminum electrode wiring formed on the silicon oxide film. Since there is no fear that the electrode wiring will be cut, the yield of element formation is also improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a bipolar integrated circuit formed by a conventional method, FIGS. 2 to 8 are cross-sectional views of transistor regions of bipolar integrated circuits formed by a conventional method, and FIGS. The figures are cross-sectional views of transistor regions of bipolar integrated circuits according to the present invention. 1: P-type substrate, 2: epitaxial layer, 3:
Embedded layer, 4: base region, 5: emitter region,
6A, 6B, 6C: oxidized oxide film, 7: element isolation layer, 8: silicon oxide film, 9: silicon nitride film,
10: silicon oxide layer, 11: silicon oxide layer, 12: high concentration P-type layer, 13: high concentration n-type layer,
14: Inter-element isolation zone region, 15: Collector electrode connection region, 16: Silicon oxide film, 17: Photoresist film, 18: P-type high concentration layer, 19: Base region, 31: Buried layer, 32: P-type silicon substrate ,
33: Epitaxial layer, 34A, 34B, 34
C: silicon nitride film, 35: silicon oxide film, 3
6: Epi layer surface, 37: P-type high concentration layer, 38: n
type high concentration layer, 39: element isolation zone region, 40: collector electrode connection region, 41A, 41B: silicon oxide film.

Claims (1)

[Claims] 1. Forming a silicon nitride film in a predetermined pattern on a region where a semiconductor element is to be formed in a silicon epitaxial layer formed on a silicon substrate and on a region where an isolation band having a conductivity type opposite to that of the epitaxial layer is to be formed; forming a silicon oxide film on the surface of the remaining epitaxial layer using the silicon nitride film as a mask; removing only the silicon nitride film on the region where the isolation band is to be formed; In the step of adding a predetermined impurity to the region where the isolation zone is to be formed using the silicon nitride film as a mask, and in the heat treatment step of diffusing the impurity into the epitaxial layer, on the region from which the silicon nitride film is removed, including the isolation zone region. 1. A method of manufacturing a semiconductor device, comprising the step of forming a silicon oxide film.