JPS6239874B2 - - Google Patents
Info
- Publication number
- JPS6239874B2 JPS6239874B2 JP56045481A JP4548181A JPS6239874B2 JP S6239874 B2 JPS6239874 B2 JP S6239874B2 JP 56045481 A JP56045481 A JP 56045481A JP 4548181 A JP4548181 A JP 4548181A JP S6239874 B2 JPS6239874 B2 JP S6239874B2
- Authority
- JP
- Japan
- Prior art keywords
- secam
- pal
- output
- signal
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
- H04N11/18—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous and sequential signals, e.g. SECAM-system
- H04N11/186—Decoding means therefor
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】
本発明は、SECAM並びにPAL両方式のカラー
テレビ放送を、選択し受信するカラー受像機の位
相歪み補正装置に関するものである。SECAM並
びにPAL両方式のカラー画像再生には周知のよ
うに水平周期（以下「1H」と呼ぶ）の遅延回路
が必要である。そこで、そのための遅延線を共用
する場合が考えられる。しかし、PAL方式受像
時とSECAM方式受像時とでは遅延信号の取り出
し方法が異なるため、SECAM受像時の1H遅延信
号に、位相の異つた信号が重畳されることになつ
て、カラー画質を損なう欠点があつた。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase distortion correction device for a color receiver that selects and receives both SECAM and PAL color television broadcasts. As is well known, a horizontal period (hereinafter referred to as "1H") delay circuit is required for color image reproduction using both SECAM and PAL systems. Therefore, a case may be considered in which a delay line for this purpose is shared. However, since the method of extracting the delayed signal is different when receiving images using the PAL method and when receiving images using the SECAM method, a signal with a different phase is superimposed on the 1H delayed signal when receiving SECAM images, which deteriorates color image quality. It was hot.
本発明は、上述の欠点を解消するために開発さ
れた位相歪み補正装置に関するものである。 The present invention relates to a phase distortion correction device developed to eliminate the above-mentioned drawbacks.
まず、ここで添付図面にもとづき従来例を説明
すると、１は入力ラインで、この入力ラインに
は、PAL放送のクロマ信号PCが入力される。２
も入力ラインで、この入力ラインにはSECAM放
送のクロマ信号SCが入力される。３は電子式の
切り換えスイツチで、このスイツチはPAL放送
受像時にライン４，５の両方に、PAL放送のク
ロマ信号PCをそれぞれ出力し、SECAM放送受
像時には一方のライン４のみにSECAM放送のク
ロマ信号SCを出力する。 First, a conventional example will be explained based on the attached drawings. Reference numeral 1 denotes an input line, and a chroma signal PC of PAL broadcasting is input to this input line. 2
is also an input line, and the SECAM broadcast chroma signal SC is input to this input line. 3 is an electronic changeover switch. This switch outputs the PAL broadcast chroma signal PC to both lines 4 and 5 when receiving a PAL broadcast, and outputs the SECAM broadcast chroma signal to only one line 4 when receiving a SECAM broadcast. Output SC.
９はライン４に直列に接続されると共に接地さ
れる抵抗器、８はインダクタンスで、このインダ
クタンスは抵抗器９に並列に接続される。 A resistor 9 is connected in series with the line 4 and grounded, and an inductance 8 is connected in parallel to the resistor 9.
６は１水平周期すなわち1Hの遅延線で、この
遅延線はインダクタンス８に並列に接続されて、
２つの入力端子Ａ，Ｂならびに２つの出力端子
Ｃ，Ｄを有し、入力信号を1H遅延させて出力端
子Ｃ−Ｄ間に出力する。 6 is a delay line of one horizontal period, that is, 1H, and this delay line is connected in parallel with inductance 8,
It has two input terminals A, B and two output terminals C, D, and outputs the input signal delayed by 1H between output terminals C and D.
１０は加減算器であるインダクタンスで、この
インダクタンスは1Hの遅延線６の出力端子Ｃ−
Ｄ間に並列接続される。１１は抵抗器で、この抵
抗器はインダクタンス１０に並列に接続される。 10 is an inductance which is an adder/subtractor, and this inductance is connected to the output terminal C- of the 1H delay line 6.
D and connected in parallel. 11 is a resistor, and this resistor is connected in parallel with the inductance 10.
なお、抵抗器９，１１ならびにインダクタンス
８，１０は、1Hの遅延線６の整合用である。 Note that the resistors 9 and 11 and the inductances 8 and 10 are for matching the 1H delay line 6.
７はキヤパシタで、このキヤパシタはライン５
に直列に接続されると共に、コイル１０の中央に
接続される。 7 is a capacitor, this capacitor is line 5
and the center of the coil 10.
上述の構成からなる回路装置において、いま、
PAL放送を受信したとすると、入力ライン１に
クロマ信号PCが入力されて、スイツチ３により
２つのライン４，５にPAL放送のクロマ信号PC
がそれぞれ出力される。ライン４に出力されたク
ロマ信号PCは、1Hの遅延線６の入力端子Ａに入
力されて、出力端子Ｃ−Ｄ間に1H遅れたクロマ
信号PCUが出力される。このクロマ信号PCU
は、第２図に示すような正弦波で現われるので出
力端子Ｃ及びＤには、正の波形及び負の波形で出
力される。今、仮に出力端子Ｃが正の波形、出力
端子Ｄには負の波形が出力されているとする。 In the circuit device having the above configuration, now,
When a PAL broadcast is received, the chroma signal PC is input to input line 1, and the chroma signal PC of the PAL broadcast is input to the two lines 4 and 5 by switch 3.
are output respectively. The chroma signal PC output to the line 4 is input to the input terminal A of the 1H delay line 6, and the chroma signal PCU delayed by 1H is output between the output terminals CD. This chroma signal PCU
appears as a sine wave as shown in FIG. 2, so it is output to output terminals C and D as a positive waveform and a negative waveform. Assume now that output terminal C is outputting a positive waveform, and output terminal D is outputting a negative waveform.
一方、ライン５に出力されたクロマ信号PC
は、キヤパシタ７を介在して、コイル１０の中点
に出力される。そして、出力端子Ｃとコイル１０
の接続点でクロマ信号PCと正のクロマ信号PCU
とが加算されライン１２にクロマ信号PC′として
出力される。また、出力端子Ｄとコイル１０の接
続点でクロマ信号PCと負のクロマ信号PCUとが
加算されライン１３にクロマ信号PCU′として出
力される。なお、ライン１２，１３に出力された
信号ｐ，ｐは、そろぞれPAL放送信号の復調回
路（図示省略）に入力され再生される。 On the other hand, the chroma signal PC output to line 5
is output to the midpoint of the coil 10 via the capacitor 7. Then, output terminal C and coil 10
At the connection point of chroma signal PC and positive chroma signal PCU
are added and output on line 12 as a chroma signal PC'. Further, at the connection point between the output terminal D and the coil 10, the chroma signal PC and the negative chroma signal PCU are added and outputted to the line 13 as the chroma signal PCU'. Note that the signals p and p output to lines 12 and 13 are respectively input to a PAL broadcast signal demodulation circuit (not shown) and reproduced.
つぎに、SECAM放送を受信したとすると、ラ
イン２に入力されたクロマ信号SCは、スイツチ
３の介在してひとつのライン４に出力される。 Next, when SECAM broadcasting is received, the chroma signal SC input to line 2 is output to one line 4 via switch 3.
したがつて、1Hの遅延線６の出力端子Ｃ−Ｄ
間には、1H遅れたクロマ信号SCUが出力され
る。この時、出力端子Ｃ−Ｄ間に出力される1H
遅れたクロマ信号SCUは、PAL受信時の説明と
同様に正弦波として出力される。したがつて、出
力端子Ｃ−Ｄ間には、正の波形のクロマ信号と負
の波形のクロマ信号とが出力される。このため、
インダクタンス１０による位相歪みと１対のライ
ン１２，１３間に存在する浮遊キヤパシタンス１
２′によつて、位相歪みが生じる。この結果、ラ
イン１４から出力される遅延された信号Ｓは、位
相歪みを有することになつて、SECAM方式の放
送受信時の再生信号を損うことになる。 Therefore, the output terminal C-D of the delay line 6 of 1H
In between, the chroma signal SCU delayed by 1H is output. At this time, 1H is output between output terminals C and D.
The delayed chroma signal SCU is output as a sine wave, similar to the explanation for PAL reception. Therefore, a chroma signal with a positive waveform and a chroma signal with a negative waveform are output between the output terminals CD. For this reason,
Phase distortion due to inductance 10 and stray capacitance 1 existing between a pair of lines 12 and 13
2' causes phase distortion. As a result, the delayed signal S output from the line 14 has phase distortion, which impairs the reproduced signal when receiving SECAM broadcasting.
本発明は、上述の欠点を解消するために開発さ
れたものである。第１図において本発明は、たと
えば、1Hの遅延線６の出力端子Ｃと基準電位点
との間にスイツチング用のトランジスタ１７を接
続している。そして、このトランジスタ１７のベ
ースに抵抗器１６と定電圧ダイオード１５の直列
回路を接続した回路構成を特徴とするものであ
る。 The present invention has been developed to overcome the above-mentioned drawbacks. In FIG. 1, in the present invention, for example, a switching transistor 17 is connected between the output terminal C of the 1H delay line 6 and a reference potential point. The circuit configuration is characterized in that a series circuit of a resistor 16 and a constant voltage diode 15 is connected to the base of the transistor 17.
上述の構成において、SECAM方式の放送受信
時であることを示す信号Sr、例えばカラーキラ
ー出力が入力端子１８に現われる。この制御電圧
が定電圧ダイオード１５のツエナ電位を越えたと
きトランジスタ１７がオンし、1Hの遅延線６の
出力端子Ｃ側に得られる遅延された信号SCUを
アースする。その結果として、インダクタンス並
びに浮遊キヤパシタを通してライン１４側に回り
込む信号が無くなり前述の位相歪の発生を防止で
きることになる。したがつて、SECAM放送受信
時に良好なクロマの遅延信号を得ることができ
る。 In the above-described configuration, a signal Sr, for example, a color killer output, indicating that SECAM broadcasting is being received appears at the input terminal 18. When this control voltage exceeds the Zener potential of the constant voltage diode 15, the transistor 17 is turned on, and the delayed signal SCU obtained at the output terminal C side of the 1H delay line 6 is grounded. As a result, there is no signal that goes around to the line 14 side through the inductance and floating capacitor, and the above-mentioned phase distortion can be prevented from occurring. Therefore, it is possible to obtain a good chroma delay signal when receiving SECAM broadcasting.
第１図は本発明の一実施例を示す電子回路図で
ある。第２図は1H遅延線の出力端子Ｃ−Ｄ間に
出力されるクロマ信号PCU及びSCUの電圧波形
である。
３……スイツチ、６……1Hの遅延線、１７…
…スイツチング用のトランジスタ。
FIG. 1 is an electronic circuit diagram showing one embodiment of the present invention. FIG. 2 shows the voltage waveforms of the chroma signals PCU and SCU output between the output terminals C and D of the 1H delay line. 3...Switch, 6...1H delay line, 17...
...Transistor for switching.
Claims (1)
送を選択して受像し、SECAM・PAL両方式の色
信号を復調する手段として一水平周期の遅延手段
をSECAM・PAL両方式の信号路として共用する
回路配置を持つカラーテレビ受像機に於て、
PAL方式の色信号の出力を取出す上記遅延手段
の一対の出力端子のうちSECAM方式の放送受像
時に用いない側に現われる信号を、SECAM方式
の放送を受像していることを示す信号に応答して
基準電位点に側路されるスイツチング回路を設け
たことを特徴とするカラーテレビ受像機の位相歪
み補正装置。1. A circuit arrangement that selects and receives both SECAM and PAL color television broadcasts and uses one horizontal period delay means as a signal path for both SECAM and PAL as a means for demodulating color signals of both SECAM and PAL. In color television receivers with
Of the pair of output terminals of the delay means for outputting PAL color signals, the signal appearing on the side that is not used when receiving SECAM broadcasting is transmitted in response to a signal indicating that SECAM broadcasting is being received. A phase distortion correction device for a color television receiver, characterized in that a switching circuit is provided that is bypassed to a reference potential point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4548181A JPS57160291A (en) | 1981-03-30 | 1981-03-30 | Phase distortion correcting circuit for color television receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4548181A JPS57160291A (en) | 1981-03-30 | 1981-03-30 | Phase distortion correcting circuit for color television receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57160291A JPS57160291A (en) | 1982-10-02 |
| JPS6239874B2 true JPS6239874B2 (en) | 1987-08-25 |
Family
ID=12720586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4548181A Granted JPS57160291A (en) | 1981-03-30 | 1981-03-30 | Phase distortion correcting circuit for color television receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57160291A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104592A (en) * | 1986-10-21 | 1988-05-10 | Matsushita Electric Ind Co Ltd | ultrasonic delay line |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS535529A (en) * | 1976-07-05 | 1978-01-19 | Toshiba Corp | Pal/secam common signal processor |
-
1981
- 1981-03-30 JP JP4548181A patent/JPS57160291A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57160291A (en) | 1982-10-02 |
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