JPS6239936A - Access control system for loop network - Google Patents

Abstract

PURPOSE:To avoid increasing of delay time of a packet switching signal even when line switching signals are in overload state and to provide flexibility for load fluctuation of the packet switching signals by so forming the titled system that the first and second limit-values of the number of usable slots based on a measured value. CONSTITUTION:In register circuits 30, 31-32, the measured value of delay time of packet switching signals corresponding to resprective communication nodes are stored through signals 200 from a reception buffer. An arithmetic circuit 33 always fetches the delay time transmitted from respective communication nodes regularly at a constant period, and calculates the average delay time of packet switching signals over the the entire loop network. The circuit 33 also determines, based on said average delay time, the first limit-value of the number of usable slots N1 and the second one N2. Based on said values N1 and N2, respective communication nodes execute the control of access to the loop network.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an access control system for a Lugu network, that is, a switching system that integrally exchanges circuit switching signals for real-time services and packet switching signals for waiting services. During configuration,
Particularly related to access control systems configured using loop networks [Prior art and its problems] In recent years, local area networks that integrally transmit and exchange circuit-switched signals and packet-switched signals have been gathered.

Among these, a system in which multiple communication nodes called switch modules are connected by a loop network is known as a switch configuration system (Technical Report of Institute of Electronics and Communication Engineers).
5E83-148) 0 In this system, switching operations are realized by sending and receiving circuit switching signals and packet switching signals between nodes via a loop network.

The access 7j to the loop Φ network consists of a plurality of slots (S+) on the loop as shown in FIG.

This is performed by providing a frame consisting of S2..., Sn.

Each slot has a slot display section Sl, a destination node address section DA, and a one-shot node address section SA.

The circuit switching signal, the packet switching signal, or the inter-node switching control signal for setting up a call for both signals is divided and stored in the information section according to the required transmission speed.

The slot display section 81 is used to identify slot usage status of vacant slots, circuit switching signals, packet conversion signals, and inter-node switching control signals.Circuit switching signals, packet switching signals, etc. are subdivided into slot sizes and are displayed as required. It is transmitted on a loop using several empty slots.

However, in this case, in order to satisfy the immediacy of the signal, each node gives the signal the highest priority and sends it out to the loop. Further, when the number of slots required for superstitions is to be increased as the number of calls increases, for example, a hunt for empty slots is performed.

Once the required number of slots are successfully completed, the required number of slots can be automatically secured in double periods based on the following principle. In other words, the empty slots to be ignored include those that become vacant due to reception at the own node, and if the circuit-switched signal is bidirectional symmetric communication, the number of slots required for transmitting the signal is This is because, at least, the double period is ensured by releasing the receiving slot from the partner node regarding the reverse call. -Packet exchange signals and inter-node exchange control signals that are allowed to wait can be performed while waiting for an empty space on the second priority signal.

FIG. 4 shows this basic configuration, in which node ($1) 39° (#2
)4 0, (#3)41, ('#4)4
2, (15243, and ('#6) 44 are connected.Each node adds the slot display section and the originating/destination node address to the circuit switched signal, multiplexes it onto the slot in the frame, and sends it to the insertion circuit. A serial queue is created for the multiplexing circuit 37 that sends the multiplexed signal to 12 and the packet switching signal that is the waiting call, and transmission control procedures such as adding the originating and arriving node rearrangement to the slot display section are carried out, A transmission buffer 15 that sends signals to the insertion circuit 12 as necessary.
, an insertion circuit 12 that inserts a packet-switched signal from its own node into an empty slot in accordance with instructions from a control circuit 13 into the multiplexed line-switched signal; and an insertion circuit 12 that detects a slot signal addressed to its own node from the loop. The Lugoo interface 1 sends signals to the branch circuit 14, receives signals from the insertion circuit 12, sends signals addressed to its own node for empty slots to the loop, and further sends empty slot position information to the control circuit 13.
1, receives a signal addressed to its own node from the loop interface 11, reads the slot display section SI, and separates the circuit switching signal, packet switching signal, and inter-node switching control signal into a separating circuit 38. Receive buffer 17. A branch circuit 14 that sends out data to the control circuit 13, a separation circuit 38 that functions in the opposite direction to the multiplexing circuit 37, a reception buffer 17 that functions in the opposite direction to the transmission buffer 15, a multiplexing circuit 37, and a separation circuit 38. Sends slot position information to be used,
Sends slot position information addressed to the own node or not used for communication between other nodes to the insertion circuit 12, receives an inter-node exchange control signal from the branch circuit 14 and sends it to the insertion circuit 12, and further and a control line (9) and a control line 13 for controlling call setting.

FIG. 5 is a diagram illustrating an example of the operation of the communication method based on the access method of the present Rouge network. In this example, a received signal from the loop (a) and a transmitted signal to the loop (b) are shown from node #1) 39 to node (#4) 13t, respectively. Further, for example, 2/1 indicates a signal from node #2 to node #1, C8 indicates a circuit switching signal, and PS indicates a packet switching signal. For example, note #1)39 received a circuit switching signal addressed to its own node from node #2 in slot S1, so it took in that slot and instead sent it from its own node in the opposite direction to node (#2).
) Sends the same signal addressed to 40 using the same slot, and since slot S2 is empty, it sends a packet exchange signal to node #3, and as for slot S3, it is passed through as it is not related to its own node. , the slot 84 takes in the packet exchange signal from the node (#5) 43 as it is sublayered, and instead sends the same signal addressed to the node (#6) 44, and the slot) 85 receives the packet from the node #4. An exchange signal is received, but since there is no new signal to be loaded, the slot is left unused and empty, and the operation is repeated.

However, in the above dynamic ffF= explanation, the inter-node exchange control signal has been omitted for simplicity.

Therefore, the operating principle of the above system is that when there is an overload of inter-switched signal calls, slots cannot be secured for bucket-if-switched signals, resulting in longer delay times and lower service quality. There was a problem. To solve this problem, the Honda 2 system sets a first usage slot number limit Nl and a second usage slot number limit N2 for the retrospective exchange signal in advance, as shown in Figure 6. , in each of the communication nodes, the total number of used slots used for circuit switching signals passing over and being sent from the own node within l frame is 11 slots, A large number of frames is set to a restricted state that prohibits the setting of a short call for circuit-switched signals from the next frame onwards.
Once the restricted state is reached, the unrestricted state is restored from the next frame onwards when the total number of slots becomes smaller than the second usage slot number limit value.

However, in this second method, since the limit value for the number of slots used is fixed, although it is possible to guarantee service quality for packet-switched signals, there is a problem in that there is no flexibility with respect to load fluctuations of packet-switched signals.

[Purpose of the invention]

An object of the present invention is to provide an integrated switch configuration for retrospective switching signals and packet switching signals using a loop network, which does not increase the delay time of packet switching signals even when circuit switching signals are overloaded. An object of the present invention is to provide an access control force formula for a loop network that is flexible with respect to load fluctuations of packet-switched signals.

[Structure of the invention]

According to the present invention, the present invention includes a communication loop, a plurality of communication nodes and one control node connected via the communication loop, a frame consisting of a plurality of slots is provided on the time axis of the communication loop, and the slots are In a loop network that integrally transmits circuit-switched signals and packet-switched signals using a loop network, each communication node measures the delay time of the packet-switched signal and notifies the control node of the delay time, and the control node measures the delay time of the packet-switched signal. Based on the value, the first and second usage slot limit values are determined and notified to each of the communication nodes, and each of the communication nodes uses them for retrospective exchange signals that pass through and are sent from the own node within one frame. When the total number of used slots is larger than the first number of used slots limit value, the setting of a new call using circuit switching signals is prohibited from the next frame onward. A loop characterized in that only when the total number of slots used for exchange signals becomes smaller than the second usage slot number limit value, the loop returns to an unregulated state in which setting of a new call is permitted from the next frame onwards.・Network access control force formula can be obtained.

[Implementation row]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are system configuration diagrams of an embodiment of a communication node and a control node according to the present invention.

In the embodiment shown in FIG. 1, the communication node is the loop interface 11. described in the conventional example. Control circuit 13, insertion circuit 12. Branch circuit 14. Transmitter, 7-10- Ayu 5. In addition to the receiving buffer 17, there are a counter circuit 16 and an adder 18. D Free Lug Frog 20. Register circuit 21
．． Set/Reset 7 Rig Frog 23° Comparison circuit 2
4. Register circuit 25. It is composed of a delay time measuring circuit 19 and a signal assembling circuit 22. However, in order to communicate other circuit-switched signals, the multiplexing circuit 371 and separation circuit 38 used in the conventional example are required, but they are omitted here for the sake of brevity.

The delay time measuring circuit 19 receives the signal +Iil! 101, the retention/transmission status of the packet exchange signal in the transmission buffer 15 is monitored, and #fill! of the signal delay time Ti (here, i is a subscript indicating a communication node) is monitored. I and transmits it to the signal assembly circuit 22 as a signal 102. The signal assembling circuit 22 inputs the delay time 102 and uses this as information to assemble it into an exchange control signal having the configuration shown in FIG. output and the insertion circuit 12. Loop interface 11 Zarani loop 10
It is transmitted to the 1fJIJ groan node. The first response to the circuit switching signal determined by the control node using the method described later.
And the second used slot limit value is conversely transmitted to each communication node via the loop 10, and is further transmitted to the loop interface 111 branch N path 14. Through the receiving buffer 17, each register circuit 21. It is stored in the register circuit 25.

The loop interface 11 newly creates a frame start pulse 107 from the signal on the loop 10 and supplies it to the counter circuit 16 and the D free lag frog 20.

The control circuit 13 supplies the power calculator 18 with the number of used slots 108 for the circuit switching signal of the second node. Branch circuit 1
4 supplies the counter circuit 16 with a detection signal 109 of a line exchanged signal between other nodes newly passing over the own node. The contents of the counter circuit 16 are cleared by the frame start pulse 107, and the counter circuit 16 counts the number of slots for circuit exchanged signaling between other nodes in the frame, and transfers the total a information to the signal 1.
Output as 10. Adder 18 receives said signal 108,1
By adding 10, a total number 111 of the number of slots used for circuit switching signals in the loop on the own node is obtained and inputted to the comparison circuit 24.

In the comparator circuit 24, the total number 111 is the first . It is compared with a second limit value for the number of used slots, and when it is larger than the first limit value, a set signal 112 is sent to the set/reset 7 rig flag 23, and when it is smaller than the second limit value, a reset signal 113 is sent to the set/reset 7 reset flag 23; The on state and the on state are respectively maintained in the frig 70 and the on state, respectively.

The on or off state signal output 114 becomes the input signal of the D free lag frog 23, and the frame start pulse signal 1
By being latched at the rising edge of 07, in the next frame described here, if the total number of slots used for circuit switching signals in the loop on the own node is larger than the first limit value, When the value is smaller than the second limit value, the state is on, and when the value is in between, the state of the previous frame is maintained, and the result is used as a regulation signal for connection of a new call of the circuit switched signal. Control circuit 13 as 115
Output to. In the control circuit 13, when the signal 102 is on, it is in a regulated state, and when it is off, it is in an unregulated state.

The functions necessary for the present invention are added to the node configuration of the example shown in FIG.
・, 32. Arithmetic circuit 33. Register circuit 34.35. A signal assembly circuit 36 is included. Register circuits 30, 31
．． . . , 32, the signal 200 is received from the receiving server and the receiving server, and the measured value Ti of the delay time of the packet exchange signal is stored corresponding to each communication node. The arithmetic circuit 33 always calculates the delay time Ill sent from each communication node,
, +112..., Tm (however, the number of communication nodes is m
) at a fixed period, and calculate the average delay time of the packet exchanged signals of the entire loop network. Further, based on the average delay time, the first usage slot number limit value Nl and the second usage slot number limit value N1 are determined, for example, as follows.

That is, the appropriate number of flight slots Nl is determined in advance for the average delay time of the entire loop network.

This can be achieved by storing N2 in each memory and referring to the memory. The first and second usage slot number limit values N! of circuit switching signals common to each new communication node obtained by this operation are obtained. and N2 are output to register circuits 34 and 35, respectively. The signal assembly circuit 36 is the signal 20
1. Input the limit values N, , N2 from 202 and use them as information to generate an exchange control signal having the configuration shown in FIG. 3, which indicates the control node address as the source node address and each communication node address as the destination node address. It is assembled for each communication node, outputted to the transmission buffer via the signal 203, and further inserted into the insertion circuit 12. Loop interface 11. It is transmitted to each communication node via the loop network 1o.

In each communication node, the limit value N,
, N, also restricts access to the loop network.
l is carried out. In this way, the total number of slots used for circuit-switched signals in the loop on each node is kept to N1 at most, so (NN1) slots are reserved for packet-switched signals that can be accessed from all nodes. Even when circuit switching signals are overloaded, there will never be any empty slots, and a fixed level of delay time, ie service quality, is guaranteed for packet switching signals and inter-node control signals. Further, by dynamically controlling the usage slot number limit values N1 and N2 instead of being fixed, a loop access system that is highly flexible with respect to load fluctuations of packet switching signals can be obtained.

〔Effect of the invention〕

As described above, in an integrated switch configuration for circuit-switched signals and packet-switched signals using a loop network, even if the circuit-switched signals are overloaded, the delay time of the packet-switched signals increases. However, it also has the effect of providing flexibility with respect to load fluctuations of packet exchanged signals.

[Brief explanation of drawings]

Fig. 2 is a block diagram of an embodiment of the same control node, Fig. 3 is a frame block diagram on a loop of the conventional line/packet integration exchange method, and Fig. 4 is a line/packet integration according to the conventional method. FIG. 5 is an explanatory diagram of the operation of the conventional system shown in FIG. 4, and FIG. 6 is an explanatory diagram of the operation of the conventional access control force type. 10... Loop, 11... Loop interface, 12... Insertion circuit, 13...
...Control circuit, 14...Branch circuit% 15...
...Transmission buffer, 16...Counter circuit, 17...Reception buffer, 18...Adder,
19...Delay time measurement circuit %2o...Dan D7
Su, Guflo, Pu, 21...Group/Register circuit, 22...
...Signal assembly circuit, 23...Set/reset, door lip 70. G, 24... Comparison circuit, 2
5...Register circuit, 30, 31.32...
...Register circuit, 33...Arithmetic circuit, 34
．． 35... Music register circuit, 36... Signal assembly circuit, 37... Multiplexing circuit, 38...
Separation circuit, 39... Node #1, 40...
... No 1 food #2, 41 ... Node #3, 42 ...
・Tsudo ST: Slo/Soto display spear 4 (T) A: Arrival note Atlus name P; SA: Yu ≦ Node Atrus ladder $ 4 Diagram No. B Coma ke procedural amendment (method) % formula % 2, Name of the invention Loop Network Access Control Method 3, Relationship with the Amendment Case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) Representative of NEC Corporation: Tadahiro Sekimoto 4, Agent: 108 Minato, Tokyo Sumitomo Sanda Building, 5-37-8, Shiba, Ward (
Contact information) NEC Corporation Patent Department) 6. Brief description of drawings in the specification subject to amendment 7. Contents of amendment

Claims (1)

[Claims] It includes a communication loop, a plurality of communication nodes and one control node connected via the communication loop, and a frame consisting of a plurality of slots is provided on the time axis of the communication loop, and the slots are used to communicate circuit-switched signals and In a loop network that integrally transmits packet-switched signals,
Each of the communication nodes measures the delay time of the packet exchanged signal and notifies the control node, and the control node calculates the first and second usage slot number limits based on the measured value and sends the result to each of the communication nodes. and if the total number of used slots used for circuit switching signals that pass through the own node and are sent from the own node within one frame in each communication node is greater than the first used slot number limit value, the following: A restriction state is set in which setting up a new call for circuit-switched signals is prohibited after the frame, and once the restriction state is reached, the total number of slots used for the circuit-switched signal is smaller than the second usage slot number limit value. An access control method for a loop network characterized by returning to an unregulated state in which setting of new calls is permitted from the next frame only when