JPS6240699A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the number of times impressing a stress voltage to the gate of a memory FET and to make the extraction of the gate difficult by dividing a train of memory cells into plural groups and maintaing a split word line of a write unnecessary train at the same level of the word line of a nonselective train of memory cells. CONSTITUTION:Word lines 5-8 are selected by a decoder 2 in the writing operation. After receiving a signal from an address buffer 12, a predecoder 12 transmits the signals COR and its inverse COR, and COL and its inverse COL to the FETs 3 and 4 for row selection and selects one word line. If all types of write information D0-D3 are '1', the predecoder 12a does not select the word lines 5a-8a of the memory train 1a by a signal of an NAND (for reduction of stress) 11a and signals of address buffers 9 and 10. This means that the word line of the train 1a is set at the same level as the nonselective word line and that no high voltage is applied. If D4-D7 are all '1', the memory train 1b is also processed in the same way. The number of times impressing the stress voltage to the gate of the memory FET is reduced and the gate is impervious to extraction.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention uses field effect transistors, particularly so-called non-volatile memory transistors that can change dark value voltage according to information and retain information for a long time. The present invention relates to a semiconductor memory device, and particularly relates to a device designed to reduce stress applied to a gate when writing information.

[Conventional technology]

Conventionally, a row (word line) selection circuit of this type of semiconductor memory device has a configuration as shown in FIG. In the figure, 1 is a memory cell array, and 2 is a decoder that selects several rows from among all the rows of the memory cell array. In this example, four rows are selected. 3.4
are row selection transistors, 5 to 8 are memory word lines, CQ-C3 and CQ-C3 are signals applied to the row selection transistors 3.4, 9.10 is a signal from the address buffer, and 12 is a signal applied to the row selection transistor 3.4. Signals CO to c3. in response to signals from the address buffer. This is a predecoder that outputs cm to C3. This pre-decoder is a two-person AND121
, two-man power AND122, 123 ., one input is negative logic.
It is composed of a two-manpower NAND 124 and inverters 125 to 132.

Next, the connection state of the transistors in the memory array is
In Figure 0 shown in the figure, the same parts as in Figure 2 are given the same symbols. TiT2 is a memory transistor in the same row, 13.14 is its control gate, 15.
16 is a floating gate, 17.18 is a source electrode, 19.20 is a drain electrode, and 21.22 is a drain line. The gate 13 of transistor T1 is electrically connected to the gate 14 of transistor T2 by a common word line 5, and similarly the gates of memory transistors on the same row are all electrically connected by a common word line. has been done.

Next, the operation will be explained. When writing to the memory transistor T1, the decoder 2 first selects word lines 5 to 8 from all word lines. On the other hand, the predecoder 12 receives the signal 9 from the address buffer.
．． 10, the signals C0 to C3 and CQ to C3 are sent to row selection transistors 3 and 4, thereby selecting only the word line where transistor 3 is on and transistor 4 is off. In this case, in order to write to the memory transistor T1, the word line 5 is selected and a high voltage is applied to it. Furthermore, a high voltage is applied to the drain line 21 as well.

Writing to the memory transistor is performed by applying a high voltage to both the gate and drain in this manner.

At this time, a memory transistor T2 whose gate is shared by the word line 5 with the memory transistor T1
A high voltage is applied to the gate 14 of the gate 14, but the drain line 2
Since no high voltage is applied to 2, writing is not performed. The same applies to other memory transistors on word line 5. Therefore, a so-called stress voltage is applied to the gate of the memory transistor on the same row as the memory transistor T1, and if the memory transistor has already been written to, there is a possibility that the gate will be pulled out.

Here, gate extraction will be explained. In FIG. 3, when writing to the memory transistor T1, it is assumed that the memory transistor T2 has already been written.

Since a high voltage is applied to the word line 5 in order to write to this memory transistor TI, a stress voltage is applied to the gate 14 of the memory transistor T2.

That is, since the memory transistor T2 has already been programmed, electrons have been injected into its floating gate 16, but the electrons are drawn toward the gate 14 by the strong electric field caused by the high voltage applied to the gate 14. There is a possibility that it will be lost. This is called gate pulling.

[Problem that the invention seeks to solve]

A conventional semiconductor memory device is configured as described above.
When writing, a stress voltage is applied to the gates of all other memory transistors on the same row as the target memory transistor.

Therefore, if for example 32 memory transistors are lined up in one row, the stress voltage will be applied as many as (32-1)-31 times at maximum, and there is a drawback that the possibility of gate pull-out is correspondingly high.

The present invention has been made to alleviate the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that is less prone to gate pull-out.

[Means for Solving the Problems] In the semiconductor storage device according to the present invention, when a memory array is divided into a plurality of blocks and writing is performed to memory transistors, blocks having no memory transistor to be written even if they are on the same row The word line is set to the same level as the non-selected word line.

[Effect]

In this invention, the memory array is divided into a plurality of blocks, and the same level as the normal selected word line level is applied only to the word line of the block to be written among the word lines of the same row. The number of times stress potential is applied to the gate of the memory transistor is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a semiconductor memory device according to an embodiment of the present invention. In the figure, la and lb are divided memory cell arrays, 2 is a decoder that selects four word lines from all the word lines of the memory array, and 3.4 are row selection transistors 5a to 13a, 5b to 8 that further select only one specific word line from among the selected word lines;
b is the divided word line, 9.10 is the signal from the address buffer, DO~D7 is the write data,
11 is write data DO to D3. N of signals D4 to D7
By performing an AND operation, the divided word line of the divided memory cell array that the memory transistor needs to write is written with the same level as the normal selected word line, and the divided word line of the divided memory cell array that the memory transistor does not need to write is written. The line has a 4-person NAN that controls the predecoder to the same level as the unselected word line and reduces the voltage applied to the memory transistor.
D (stress reduction circuit), 12a.

12b is a signal C0L-C3L, COL~C3L, COR which receives the signal 9.10 from the address buffer and the signal of the circuit 11 and sends it to the row selection transistor 3.4.
-C3R, C0R - This is a predecoder that generates C3R. In addition, in this predecoder, 133 is a three-man power A.
ND, 134, 135 are 3-man powered NAN with negative logic for 1-man power
D, 136 is a 3-person AND operation in which the 2-person operation is negative logic.

Further, FIG. 4 shows a circuit configuration of an EPROM incorporating the circuit of the above embodiment. In the figure, 22 is a row decoder, 23
24 is a column decoder, 24 is a row address buffer, 25 is a column address buffer, 26 is a sense amplifier, 27 is an input buffer, and 28 is an output buffer. Row decoder 22 of FIG. 4 includes decoder 2 of FIG. 1 and transistors 3.4. Also, the predecoder 32 in FIG.
correspond to the circuits 12a and 12b in FIG.

For example, if the EPROM has 128 word lines, one word line is selected from among 512 word lines in the vertical direction.
Select 4 word lines from the book and circuit 1
One of the four signals is selected from the two signals. That is, the circuit 12 alone cannot directly select one of the 512 word lines.

The memory cell array of EPROM is shown in FIG.

As shown in Figure 2, it is divided into eight blocks Do to D7, but when writing, one
Writing is performed simultaneously on a total of eight memory transistors.

Note that DQ-D7 is set to "O" (low) or "1" input from the data input/output terminal in FIG. 4 when writing.
” (high), and the stress reduction circuit shown in FIG.
-D3 and the circuits 11a and 11b which perform NAND of the signals D4 to D7.

Next, the operation will be explained using FIG. When writing, first, the decoder 2 selects word lines 5 to 8 from all word lines. On the other hand, the predecoder 12 receives the signal from the address buffer and C0
L-C3L, C0L-C3L.

C0R-C3R, C0R-C31? The signal is sent to the row selection transistors 3 and 4 to select one of the word lines 5 to 8, so if the write data D
If o-03 are all “1”, the predecoder 12a is N
From the signal of AND circuit (stress reduction circuit) 11a and the signal of address buffer 9.10, none of the word lines 5a to 8a of memory array 1a is selected. That is, if there is no memory transistor to be written to in the memory array 1a, the word line of the memory array 1a will be at the same level as the unselected word line,
High voltage is not applied. On the other hand, when the write data D4 to D7 of the memory array 1b are all “1”,
The same process is used.

In this way, in this embodiment, a high voltage was applied to the gates of all memory transistors in the same row as the target memory transistor during writing, but a high voltage is applied only to the memory transistors of the divided memory cell array to which the target transistor belongs. Since the stress voltage is applied, the number of times the stress voltage is applied is greatly reduced, which has the effect of making data extraction less likely to occur.

In addition, in the above embodiment, the case where the memory array is divided into two has been explained, but if the memory array is not subdivided too much, the effect of adding such functions on the complexity of the circuit and the increase in the chip area will be reduced. It can be said that there is no such thing at all.

It is also possible to further subdivide the memory cell array; in principle, the more subdivided the memory cell array is, the fewer times stress is applied to the gates of the memory transistors. That is, in the case of 2-part division, when each word has an 8-bit configuration, there are 256 possible data possibilities, and 31 of them have the effect of reducing stress.
Furthermore, if the memory cell array is divided into four to increase speed in the future, it will be effective in 175 out of 256 ways.
Great practical effects can be expected.

Of course, it is also possible to divide the memory arrays asymmetrically so that the capacity ratio of the divided memory arrays is 1:3.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, a memory cell array can be divided into a plurality of parts, and the divided word lines of the divided memory cell arrays that do not require writing can be made to the same level as the word lines of unselected memory cell arrays. This has the effect of significantly reducing the number of times stress voltage is applied to the gate of the memory transistor, and greatly reducing the possibility of gate pull-out.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional row selection circuit, FIG. 3 is a diagram showing the configuration of a memory cell array in the row direction, and FIG. 1st
FIG. 2 is a block diagram of an EPROM incorporating the circuit shown in the figure. In the figure, la and lb are divided memory cell arrays, 2 is a decoder, 5a to 8a are divided word lines, 12a and 1
2b is a predecoder (word line selection decoder), I
la and Ilb are four-person NAND (stress reduction circuit). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Nonvolatile memory transistors with floating gates covered with an insulating film are arranged in a matrix, and two
In a semiconductor memory device that writes to or reads from two or more memory transistors, the memory cell array is divided into two or more, and a word line that is the gate of the memory cell transistor and a word line selection decoder that drives the word line are connected to the memory cell array. When writing to a plurality of memory transistors in a word line selected by the decoder, the divided word line of the divided memory cell array to which the memory transistor requires writing among the selected word lines is usually divided into the same number of memory transistors. The word line selection decoder is controlled so that the divided word line of the divided memory cell array where the memory transistor does not require writing is set to the same level as the unselected word line. A semiconductor memory device characterized by being provided with a stress reduction circuit that reduces stress applied to transistors.