JPS6241114B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording device such as a wire printer or a line printer.

Wire printers, for example, which generally record letters, numbers, symbols, etc. in a dot matrix pattern, are used in computer terminals, etc., and on the other hand, they have high-speed recording performance that allows them to process large amounts of data at high density in a short period of time. On the other hand, it is required that the device be compact, inexpensive, and highly reliable for widespread use. When recording text or graphic information using the above devices, the amount of information fluctuates considerably over time.
Also, regarding the recorded content, since the dot density varies depending on the recording location, the drive output varies considerably. When used as a high-speed printer, the drive output of the recording head should be increased to drive it at a speed close to its performance limit, and even when performing high-density recording, the drive power should be increased and recording unevenness would not occur. Therefore, a large-capacity power supply, a circuit that can withstand large input/output, and a head drive mechanism that can withstand heat generation are required, making the device large and expensive, and causing reliability problems. On the other hand, when used as an inexpensive popular printer, recording is performed at a low speed, and the performance of the head is not fully utilized. In either case, recording density (number of printed dots per certain area or amount of recorded information per certain area)
Since recording is performed at a constant driving speed even though the speed varies considerably over time, the above-mentioned drawbacks arise.
However, in normal recording, high-density recording locations where recording is performed at the limit of the head's performance are only a small part of the total, and most of the recording is performed with low drive output.

Therefore, the present invention enables high-speed recording with a small-capacity power supply and inexpensive equipment by controlling the recording speed according to the number of printed dots within a certain range, thereby ensuring recording quality even in high-density recording locations. It is something.

An embodiment of the present invention will be described below based on the drawings. In FIG. 1, Bu is a buffer memory that stores one line of recorded data.
CG is a drive signal generator consisting of a character generator and a control circuit for representing a character pattern read out from this character generator and for reading a print element drive signal for driving a print element; Dr ₁ is a drive signal generator; Coil _L1 ...This is a drive circuit for _L7 . The coils _L1 ... _L7 are for driving printing wires (not shown) which are printing elements, and in this example, seven printing wires are arranged in the paper feeding direction. M ₁ , M ₂ are one shot multi, F ₀ ,
F ₁ and F ₂ are flip-flop circuits, E ₁ is an inverter, and G ₁ . . . G ₄ is a gate circuit. C ₀ is a counter, D is a variable frequency divider, and this variable frequency divider D
A control means is constituted by a flip-flop circuit _F2 and the like. _Dfr2 is a drive circuit that drives the motor M for feeding the head.
_R1 ... _R10 is a resistor, C is a capacitor, _D1 ... _D7 is a diode, _Tr1 , _Tr2 are transistors,
Flip-flop circuit with transistor Tr ₁ resistor R _8
F1 etc. constitute a detection means. The capacitor C, diodes D ₁ to D ₇ and resistors R ₁ to _{R 7} constitute a counting means. Resistors FR ₁ ......R ₇ are all set to the same resistance value.

Next, before describing the operation, the permissible level of recording density and the setting of the power supply capacity will be explained.

First, the permissible level of recording density is set in advance as follows based on the relationship between the capacity of the power source of the head drive coil and the characteristics of the head. First, the power supply characteristics when an unregulated power supply is used are as shown in FIG. 2, where V indicates the power supply voltage and T indicates the energization time. Voltage Vo is the power supply voltage in a no-load state, and voltage Vn is the minimum voltage required to drive the coil normally. Therefore, a load with a reasonable margin compared to the average load in normal recording.
Wn is determined as an allowable load, and the capacity of the power supply is determined so that the power supply voltage will not drop below the voltage Vn even if this load Wn is applied in one row in succession as shown by the curve ln in FIG. In addition, the instantaneous maximum load when all pins are driven simultaneously is W ₁ , and this load W ₁ can be continuously recorded for a time T ₁ (that is, n digits) as shown in the curve l 1 in Figure ₂ . This determines the capacity of the power supply. The time T ₁ to withstand this maximum load W ₁ is set to a time that allows continuous recording of several digits, for example, since if it is too short, problems such as deterioration of recording quality due to voltage fluctuations and damage to the head will occur.

Note that when a constant voltage circuit is used as a power source, there is no voltage fluctuation as described above, but the constant voltage circuit will be damaged in an overload state. Therefore, in this case, the allowable load Wn is determined according to the heat generation of the power supply components, the average power amount, and the heat generation amount of the drive coil, and the maximum load W ₁ and the time to withstand this T ₁ (n digit) are determined by the power supply components. It is determined based on the short-term maximum rating of (for example, fuses, transistors, rectifiers, etc.).

Now, the recording density can be detected by dividing one line into a plurality of blocks of n lines each and detecting the number of printed dots in each n column. Then, this recording density is compared with a preset tolerance level, and if there is a part that exceeds the tolerance level, that one line is recorded at low speed, and if all of the lines are below the tolerance level, recording is performed at high speed. It is something.

Next, the operation will be explained. It is assumed that flip-flop circuits F ₀ , F ₁ , and F ₂ are reset in the initial state. First, recording data is input from terminal P ₁ , and when one line of recording data is stored in the buffer memory Bu, a data input end signal is supplied to terminal P ₂ , and one shot multi M ₁ is triggered, as shown in FIG. An output pulse is generated as shown in A,
Supplied to gate circuit _G2 . The input terminal _P3 of the gate circuit _G2 is set to “1” by the output of the inverter _E1 .
Since it is held at , gate circuit G ₂ opens,
A clock pulse from terminal CL passes as shown in FIG. 3B. This clock pulse is a gate circuit.
The print element is supplied to the buffer register Bu and the drive signal generator CG via _G1 , represents the character pattern of the first digit character in the one line of recorded data, and drives the print element. The drive signal is the first
The signals are sequentially read out from the column and are generated at the output terminals q ₁ ... q ₇ of the drive signal generator CG. At this time, since the output terminal _P5 of the gate circuit _G4 is held at "0" by the output of the flip-flop circuit _F2 , the drive circuit
Dr ₁ and Dr ₂ are kept inactive.

Next, the operation of counting the number of printed dots for every n digits will be described.

On the other hand, printing element drive signals from terminals q _{1 .} . _. q 7 are supplied to capacitor C via diodes D ₁ . _{. .} D ₇ and resistors R ₁ . That is, for the first digit, the number of dots recorded in the first column is converted into an analog voltage and the capacitor C is charged. At this time, transistor Tr ₂ is kept off. For example, when only terminal q ₁ is "1", integration is performed with a time constant determined by resistor R ₁ and capacitor C, but when terminals q ₁ and q ₂ are "1", resistor R ₁ ,
R ₂ is connected in parallel, and the time constant of the integrating circuit becomes 1/2 of the above value. Therefore, the integrated output is a voltage corresponding to the number of dots recorded.
A second column printing element drive signal is then generated from the drive signal generator CG, and the number of recorded dots is converted to an analog voltage and integrated or counted in exactly the same manner as above. In this way, the printing element drive signals of each column are sequentially read out and added one after another.
When the digit is completed, the printing element drive signal for the second digit character is sequentially read out in the same manner as described above by the next clock pulse from the gate circuit _G2 , and integration is performed according to the number of printed dots. The integrated output increases according to the number of dots as shown in FIG. 3C. On the other hand, ring counter C ₀ is gate circuit G ₂
The above-mentioned clock pulses are counted, that is, the number of digits that are currently being read is counted, and an output is generated when the previously set n digits of data are read out. This triggers the one-shot multiplier _M3 , producing a pulse as shown in FIG. 3D, turning on the transistor _Tr2 and discharging the capacitor C. At this time, the gate circuit _G2 is closed by the output of the inverter _E1 , and the clock pulse is stopped. This operation is repeated every n digits, and when the number of printed dots in each n digit is below the allowable level, the above integral output is shown in Figure 3C.
The setting is made so that the reference voltage V ₀ of the transistor Tr 1 is not reached and the transistor Tr ₁ is kept off. Also, if the number of printed dots exceeds the permissible level, the integral output will change to voltage.
Set it so that V ₀ is reached and transistor Tr ₁ is turned on. The gate circuit _G3 is now open by the output of the flip-flop circuit _F1 , and the clock pulse from the terminal CP is supplied to the flip-flop circuit _F1 as shown in FIG. 3E. However _, since the first and _second integral outputs in _FIG . Its output Q,
remain held at "0" and "1", respectively. And the third integrated output in Figure 3C is the voltage
When V ₀ is exceeded, transistor Tr ₁ turns on,
The D input of the flip-flop circuit _F1 is inverted to "1". Now, the clock pulse shown in FIG. 3E is supplied to the terminal CP of the gate circuit _G3 , so that the output Q of the flip-flop circuit _F1 becomes as shown in FIG.
At the same time, the output is inverted to "0" and the gate circuit _G3 is closed. Therefore, the clock pulse from the gate circuit _G3 stops as shown in Figure 3E, and from then on, the clock pulse is stopped from the flip-flop circuit.
The output Q of _F1 remains at "1" and "0", respectively. In other words, if there is even one location in one line where the number of printed dots within n digits exceeds the permissible level, the flip-flop circuit _F1
The outputs Q, are held at "1" and "0", respectively. As a result, the frequency division ratio of the variable frequency divider D is specified as shown below, and the recording speed for one line is specified.

When all the data for one row is read out in this way, the output pulse of one-shot multi _M1 is the third one.
The circuit stops as shown in FIG. 3A, and as the gate circuit _G2 closes, the flip-flop circuit _F0 is triggered to produce an output as shown in FIG. 3G. This output releases the reset of the variable frequency divider D, triggers the flip-flop circuit _F2 , and its output Q opens the gate circuit _G4 . The variable frequency divider D has a frequency division ratio designated by the output of the flip-flop circuit _F1 , and produces the output pulse shown in FIG. 3H in response to a clock pulse from the terminal CP. This output pulse is supplied to the drive circuit Dr ₂ via the gate circuit G ₄ to drive the motor M and send the head. This feed rate is set, for example, to 1/2 of the normal feed rate. On the other hand, the above pulse from terminal _P5 is the drive circuit
It is supplied to the buffer register Bu and _the drive signal generator CG via the gate circuit _G1 . As a result, the data for one line is read out again from the buffer register Bu in synchronization with the feeding of the head, and the data is read out from the drive circuit Dr ₁ to the coil L in accordance with the printing element drive signal from the drive signal generator CG. ₁ ...The driving output of _L7 is selectively generated, the printing wire is driven, and recording is performed.

By the way, if the number of printed dots per n digits is below the permissible level over the entire line, the output Q of the flip-flop circuit _F1 remains at "0". As a result, the frequency division ratio of the variable frequency divider D becomes 1/2 of the above value.

Therefore, as shown in FIG. 3I, the variable frequency divider D generates a pulse having twice the above-mentioned frequency, and recording is performed at twice the above-mentioned speed.

As described above, in this example, the recording speed is divided into two stages, and a line containing a block in which the number of printed dots within n digits exceeds the permissible level is recorded at half the normal speed. When the recording speed is halved,
Since the actual load on the power supply is reduced by half, the recording quality of high-density recording areas can also be compensated.

Next, other embodiments will be described.

In FIG. 4, SR is a shift register and Ca is a counter, which constitute a counting means. A is a discrimination circuit, and this and a flip-flop circuit _F1 etc. constitute a detection means.
Cb and Cc are counters, B is a coincidence circuit, F ₃ and F ₄ are flip-flop circuits, K is a reset circuit, G ₅ ...
... _G9 is a gate circuit, and _E2 is an inverter.

Note that the same reference numerals as in FIG. 1 indicate the same things.

Next, the operation will be explained. When one line of recording data is sequentially supplied from terminal _P1 , it is written to the buffer memory Bu and also written to the counter.
A writing strobe pulse is supplied to Cb,
Counter Cb counts the number of digits of recorded data written to buffer memory Bu. That is, it counts the number of the last digit to be recorded in one line. In this case, if there are blank digits in the middle, these are also included in the number of digits. Then, the data input end signal arrives at the terminal _P2 , the outputs Q of the flip-flop circuits _F3 and _F4 are inverted to "1", and one input of the gate circuits _G8 and _G9 is held at "1". Gate record G ₆ opens and the clock pulse passes. With this one pulse, a print element drive signal representing a character pattern of one digit of characters is read out from the drive signal generator CG in the following manner as in the above embodiment.

From the control circuit in the drive signal generator CG, the above 1
The pulse generates the pulses shown in Figure 5A for the number of columns (including spaces) that make up one digit, and this one
The printing element drive signal is sequentially read out from the first column within the one digit for each pulse. The pulses of FIG. 5A are level inverted and supplied to the gate circuit G ₉ as shown in FIG. 5B, so that the pulses from the terminal CP are generated from the gate circuit G ₉ as shown in FIG. 5C. In other words, _the first pulse shown in FIG _.
is read into the shift register SR, and immediately after that, a pulse from the gate circuit G9 to the terminal Cp is read from the gate circuit _G9 to the shift register SR.
A pulse is generated, and the printing element drive signal in the shift register SR is serially shifted and read out.

For example, if the printing element drive signal (1110010) of the shift register SR is, the pulse of FIG. 6A (enlarged pulse of FIG. 5C) from the gate circuit _G9 causes the shift register SR to output The printing element drive signal is read out as shown in Fig. 6B, and the number corresponding to the printing element drive signal "1" is output from the gate circuit _G5 by this printing element drive signal and the above-mentioned pulse as shown in Fig. 6C. A pulse occurs,
It is counted by counter Ca. In other words, in the above embodiment, the number of printed dots was detected by converting the number of dots into an analog voltage, but in this example, the number of printed dots is detected by converting the number of dots into an analog voltage.
It is counted digitally by Ca.

By the way, the above clock pulse from terminal _P4 is supplied to ring counters Co and Co, and the number of digits is counted. The ring counter Co produces an output every n digits, and the counter Cc counts the number of digits for one line.

Now, when the counter Ca counts the number of printed dots for n digits, an output is generated from the link counter Co as in the above embodiment, and the one shot multi M ₃
is triggered, and the discrimination circuit A is activated by its output pulse. The determination circuit A compares the contents of the counter Ca with a preset value. In other words, it is determined whether the number of printed dots is below the allowable level or not, and when the number of printed dots exceeds the allowable level, the output of the judgment circuit A is set to "1", and when it is below the allowable level, it becomes "0". There is. Therefore, similarly to the above embodiment, if there is a block in one line in which the number of printed dots for n digits exceeds the permissible level, the output Q of the flip-flop circuit _F1 becomes "1".
is held, and the frequency division ratio of frequency divider D is specified.

Note that when the above-mentioned determination is completed, the output pulse of the one-shot multi _M3 is stopped, and the content of the counter Ca is cleared by the output of the reset circuit K. When all of the recorded data for one line is read out, the contents of the counter Cc match the contents of the counter Cb, and an output is generated from the matching circuit B. This output is connected to the flip-flop circuit via the gate circuit _G7 .
Reset _F3 . Therefore, gate circuits G ₆ , G ₉
is closed and the gate circuit _G8 is opened, the reset of the frequency divider D is released, and the flip-flop circuit _F2 is further triggered. Therefore, the pulse from the frequency divider D passes through the gate circuits G ₄ , G ₃ , and G ₁ , drives the motor M, and sends the head, and in synchronization with this, the above-mentioned one row of data is sequentially read out. The print wire is driven by the output of the drive circuit Dr ₁ .

When the recording for the above line is finished, the terminal
A recording end signal is supplied to RE, and the flip-flop circuits _F1 to _F4 and counters Ca, Cb, Cc, etc. are reset to their initial states, and the next row can be recorded in exactly the same manner as described above.

Incidentally, in each of the above embodiments, the recording speed is divided into two stages, but the recording speed is not limited to this, and it is also possible to divide it into three or more stages as necessary. In this case, in the embodiment shown in FIG. 1, the bias voltages of the transistors of the number corresponding to the number of stages are made different, the base of each transistor is commonly connected to the capacitor C, and the output of each transistor is connected to the corresponding flip-flop circuit. supply to. Then, the frequency division ratio of the frequency divider D can be designated by the output of each flip-flop circuit.

Further, in the embodiment shown in FIG. 4, the contents of each count of the counter Ca corresponding to the number of printed dots at each stage are determined by a discrimination circuit, and each discrimination output is recorded in the corresponding flip-flop circuit.

Furthermore, as described above, the present invention is not limited to wire printers, and may be used in discharge breakdown printers, line printers, and the like. In the case of a line printer, for example, the amount of information for several lines may be detected in advance and the recording speed may be controlled according to the amount of information.

As detailed above, according to the present invention, one line is n
The number of printing dots in each block divided into blocks of digits each is counted, and the printing speed for one line is selected according to the number of printing dots in the block with the maximum number of printing dots in one line. Even in high-density recording locations, average power consumption can be reduced and recording quality can be compensated. Therefore, a small-capacity power source and an inexpensive drive device are required. Furthermore, even in lines containing a mixture of Chinese characters, numbers, alphanumeric characters, etc., the recording density can be determined in detail regardless of the type of characters, and printing can always be performed at the optimum speed.

In addition, in normal recording, there are only a few places where low-speed recording is required, such as consecutive high-density recording points of several orders of magnitude, and the majority can be recorded at high speed.
The total time required for recording is almost the same as that of conventional high-speed printers.

[Brief explanation of the drawing]

Figure 1 is an electric circuit diagram showing one embodiment of the present invention, Figure 2 is a power supply voltage characteristic diagram in this example, and Figure 3 is a diagram showing power supply voltage characteristics in this example.
The figure is a time chart for explaining the operation, FIG. 4 is an electric circuit diagram of another embodiment, and FIGS. 5 and 6 are time charts for explaining the operation of FIG. 4, respectively. _D1 to _D7 ...Diode, _R1 to _R10 ...Resistor, C...Capacitor, _Tr1 , _Tr2 ...Transistor, _F1 , _F2 ...
Flip-flop circuit, Co...ring counter,
M ₂ ...One-shot multi, D...Variable frequency divider, SR
...shift register, Ca...counter, A...discrimination circuit, Cb, Cc...counter, B...matching circuit, F ₃ , F ₄
...flip-flop circuit.

Claims (1)

[Scope of Claims] 1. A recording device in which a plurality of printing elements are arranged in the paper feeding direction, and each printing element is scanned in a direction perpendicular to the paper feeding direction to perform printing, in which one line is divided into n digits each. A drive signal generating means for generating a print element drive signal for representing a character pattern of each character and for driving the above-mentioned print element; and a print element drive signal from the drive signal generation means. a counting means for counting the number of printed dots necessary to print characters in each block, with the count input as a counting input; and a counting means for counting the number of printed dots required to print characters in each block; and a control means that receives the output of the detection means and selects the printing speed of one line according to the stage of the count value of the counting means in the block where the number of printed dots in one line is maximum. A recording device consisting of.